415 lines
23 KiB
C
415 lines
23 KiB
C
/****************************************************************************
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* drivers/lcd/ssd1289.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Definitions for the Solomon Systech SSD1289 LCD controller
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*
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* References: SSD1289, Rev 1.3, Apr 2007, Solomon Systech Limited
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*/
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#ifndef __DRIVERS_LCD_SSD1289_H
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#define __DRIVERS_LCD_SSD1289_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifdef CONFIG_LCD_SSD1289
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* SSD1289 Register Addresses (All with DC=1) */
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#define SSD1289_OSCSTART 0x00 /* Oscillation Start (write) */
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#define SSD1289_DEVCODE 0x00 /* Oscillation Start (read) */
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#define SSD1289_OUTCTRL 0x01 /* Driver output control */
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#define SSD1289_ACCTRL 0x02 /* LCD drive AC control */
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#define SSD1289_PWRCTRL1 0x03 /* Power control 1 */
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#define SSD1289_CMP1 0x05 /* Compare register 1 */
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#define SSD1289_CMP2 0x06 /* Compare register 2 */
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#define SSD1289_DSPCTRL 0x07 /* Display control */
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#define SSD1289_FCYCCTRL 0x0b /* Frame cycle control */
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#define SSD1289_PWRCTRL2 0x0c /* Power control 2 */
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#define SSD1289_PWRCTRL3 0x0d /* Power control 3 */
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#define SSD1289_PWRCTRL4 0x0e /* Power control 4 */
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#define SSD1289_GSTART 0x0f /* Gate scan start position */
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#define SSD1289_SLEEP 0x10 /* Sleep mode */
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#define SSD1289_ENTRY 0x11 /* Entry mode */
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#define SSD1289_OPT3 0x12 /* Optimize Access Speed 3 */
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#define SSD1289_GIFCTRL 0x15 /* Generic Interface Control */
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#define SSD1289_HPORCH 0x16 /* Horizontal Porch */
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#define SSD1289_VPORCH 0x17 /* Vertical Porch */
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#define SSD1289_PWRCTRL5 0x1e /* Power control 5 */
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#define SSD1289_DATA 0x22 /* RAM data/write data */
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#define SSD1289_WRMASK1 0x23 /* RAM write data mask 1 */
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#define SSD1289_WRMASK2 0x24 /* RAM write data mask 2 */
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#define SSD1289_FFREQ 0x25 /* Frame Frequency */
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#define SSD1289_VCOMOTP1 0x28 /* VCOM OTP */
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#define SSD1289_OPT1 0x28 /* Optimize Access Speed 1 */
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#define SSD1289_VCOMOTP2 0x29 /* VCOM OTP */
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#define SSD1289_OPT2 0x2f /* Optimize Access Speed 2 */
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#define SSD1289_GAMMA1 0x30 /* Gamma control 1 */
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#define SSD1289_GAMMA2 0x31 /* Gamma control 2 */
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#define SSD1289_GAMMA3 0x32 /* Gamma control 3 */
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#define SSD1289_GAMMA4 0x33 /* Gamma control 4 */
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#define SSD1289_GAMMA5 0x34 /* Gamma control 5 */
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#define SSD1289_GAMMA6 0x35 /* Gamma control 6 */
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#define SSD1289_GAMMA7 0x36 /* Gamma control 7 */
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#define SSD1289_GAMMA8 0x37 /* Gamma control 8 */
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#define SSD1289_GAMMA9 0x3a /* Gamma control 9 */
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#define SSD1289_GAMMA10 0x3b /* Gamma control 10 */
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#define SSD1289_VSCROLL1 0x41 /* Vertical scroll control 1 */
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#define SSD1289_VSCROLL2 0x42 /* Vertical scroll control 2 */
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#define SSD1289_HADDR 0x44 /* Horizontal RAM address position */
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#define SSD1289_VSTART 0x45 /* Vertical RAM address start position */
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#define SSD1289_VEND 0x46 /* Vertical RAM address end position */
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#define SSD1289_W1START 0x48 /* First window start */
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#define SSD1289_W1END 0x49 /* First window end */
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#define SSD1289_W2START 0x4a /* Second window start */
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#define SSD1289_W2END 0x4b /* Second window end */
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#define SSD1289_XADDR 0x4e /* Set GDDRAM X address counter */
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#define SSD1289_YADDR 0x4f /* Set GDDRAM Y address counter */
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/* SSD1289 Register Bit definitions */
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/* Index register (DC=0) */
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#define SSD1289_INDEX_MASK 0xff
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/* Device code (read) */
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#define SSD1289_DEVCODE_VALUE 0x8989
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/* Oscillation Start (write) */
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#define SSD1289_OSCSTART_OSCEN (1 << 0) /* Enable oscillator */
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/* Driver output control */
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#define SSD1289_OUTCTRL_MUX_SHIFT (0) /* Number of lines for the LCD driver */
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#define SSD1289_OUTCTRL_MUX_MASK (0x1ff << SSD1289_OUTCTRL_MUX_SHIFT)
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# define SSD1289_OUTCTRL_MUX(n) ((n) << SSD1289_OUTCTRL_MUX_SHIFT)
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#define SSD1289_OUTCTRL_TB (1 << 9) /* Selects the output shift direction of the gate driver */
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#define SSD1289_OUTCTRL_SM (1 << 10) /* Scanning order of gate driver */
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#define SSD1289_OUTCTRL_BGR (1 << 11) /* Order from RGB to BGR in 18-bit GDDRAM data */
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#define SSD1289_OUTCTRL_CAD (1 << 12) /* Retention capacitor configuration of the TFT panel */
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#define SSD1289_OUTCTRL_REV (1 << 13) /* Reversed display */
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#define SSD1289_OUTCTRL_RL (1 << 14) /* RL pin state */
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/* LCD drive AC control */
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#define SSD1289_ACCTRL_NW_SHIFT (0) /* Number of lines to alternate in N-line inversion */
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#define SSD1289_ACCTRL_NW_MASK (0xff << SSD1289_ACCTRL_NW_SHIFT)
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#define SSD1289_ACCTRL_WSMD (1 << 8) /* Waveform of WSYNC output */
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#define SSD1289_ACCTRL_EOR (1 << 9) /* EOR signals */
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#define SSD1289_ACCTRL_BC (1 << 10) /* Select the liquid crystal drive waveform */
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#define SSD1289_ACCTRL_ENWS (1 << 11) /* Enables WSYNC output pin */
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#define SSD1289_ACCTRL_FLD (1 << 12) /* Set display in interlace drive mode */
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/* Power control 1 */
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#define SSD1289_PWRCTRL1_AP_SHIFT (1) /* Current from internal operational amplifier */
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#define SSD1289_PWRCTRL1_AP_MASK (7 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_LEAST (0 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_SMALL (1 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_SMMED (2 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_MEDIUM (3 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_MEDLG (4 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_LARGE (5 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_LGMX (6 << SSD1289_PWRCTRL1_AP_SHIFT)
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# define SSD1289_PWRCTRL1_AP_MAX (7 << SSD1289_PWRCTRL1_AP_SHIFT)
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#define SSD1289_PWRCTRL1_DC_SHIFT (4) /* Set the step-up cycle of the step-up circuit for 262k-color mode */
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#define SSD1289_PWRCTRL1_DC_MASK (15 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx24 (0 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx16 (1 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx12 (2 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx8 (3 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx6 (4 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx5 (5 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx4 (6 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx3 (7 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx2 (8 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FLINEx1 (9 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FOSd4 (10 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FOSd6 (11 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FOSd8 (12 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FOSd10 (13 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FOSd12 (14 << SSD1289_PWRCTRL1_DC_SHIFT)
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# define SSD1289_PWRCTRL1_DC_FOSd16 (15 << SSD1289_PWRCTRL1_DC_SHIFT)
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#define SSD1289_PWRCTRL1_BT_SHIFT (9) /* Control the step-up factor of the step-up circuit */
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#define SSD1289_PWRCTRL1_BT_MASK (7 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p6m5 (0 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p6m4 (1 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p6m6 (2 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p5m5 (3 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p5m4 (4 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p5m3 (5 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p4m4 (6 << SSD1289_PWRCTRL1_BT_SHIFT)
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# define SSD1289_PWRCTRL1_BT_p4m3 (7 << SSD1289_PWRCTRL1_BT_SHIFT)
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#define SSD1289_PWRCTRL1_DCT_SHIFT (12) /* Step-up cycle of the step-up circuit for 8-color mode */
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#define SSD1289_PWRCTRL1_DCT_MASK (15 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx24 (0 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx16 (1 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx12 (2 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx8 (3 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx6 (4 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx5 (5 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx4 (6 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx3 (7 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx2 (8 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FLINEx1 (9 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FOSd4 (10 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FOSd6 (11 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FOSd8 (12 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FOSd10 (13 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FOSd12 (14 << SSD1289_PWRCTRL1_DCT_SHIFT)
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# define SSD1289_PWRCTRL1_DCT_FOSd16 (15 << SSD1289_PWRCTRL1_DCT_SHIFT)
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/* Compare register 1 and 2 */
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#define SSD1289_CMP1_CPG_SHIFT (2)
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#define SSD1289_CMP1_CPG_MASK (0x3f << SSD1289_CMP1_CPG_SHIFT)
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#define SSD1289_CMP1_CPR_SHIFT (10)
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#define SSD1289_CMP1_CPR_MASK (0x3f << SSD1289_CMP1_CPR_SHIFT)
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#define SSD1289_CMP2_CPB_SHIFT (2)
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#define SSD1289_CMP2_CPB_MASK (0x3f << SSD1289_CMP2_CPB_SHIFT)
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/* Display control */
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#define SSD1289_DSPCTRL_D_SHIFT (0) /* Display control */
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#define SSD1289_DSPCTRL_D_MASK (3 << SSD1289_DSPCTRL_D_SHIFT)
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# define SSD1289_DSPCTRL_OFF (0 << SSD1289_DSPCTRL_D_SHIFT)
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# define SSD1289_DSPCTRL_INTERNAL (1 << SSD1289_DSPCTRL_D_SHIFT)
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# define SSD1289_DSPCTRL_ON (3 << SSD1289_DSPCTRL_D_SHIFT)
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#define SSD1289_DSPCTRL_CM (1 << 3) /* 8-color mode setting */
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#define SSD1289_DSPCTRL_DTE (1 << 4) /* Selected gate level */
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#define SSD1289_DSPCTRL_GON (1 << 5) /* Gate off level */
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#define SSD1289_DSPCTRL_SPT (1 << 8) /* 2-division LCD drive */
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#define SSD1289_DSPCTRL_VLE_SHIFT (9) /* Vertical scroll control */
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#define SSD1289_DSPCTRL_VLE_MASK (3 << SSD1289_DSPCTRL_VLE_SHIFT)
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# define SSD1289_DSPCTRL_VLE(n) ((n) << SSD1289_DSPCTRL_VLE_SHIFT)
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#define SSD1289_DSPCTRL_PT_SHIFT (11) /* Normalize the source outputs */
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#define SSD1289_DSPCTRL_PT_MASK (3 << SSD1289_DSPCTRL_PT_SHIFT)
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# define SSD1289_DSPCTRL_PT(n) ((n) << SSD1289_DSPCTRL_PT_SHIFT)
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/* Frame cycle control */
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#define SSD1289_FCYCCTRL_RTN_SHIFT (0) /* Number of clocks in each line */
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#define SSD1289_FCYCCTRL_RTN_MASK (3 << SSD1289_FCYCCTRL_RTN_SHIFT)
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# define SSD1289_FCYCCTRL_RTN(n) (((n)-16) << SSD1289_FCYCCTRL_RTN_SHIFT)
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#define SSD1289_FCYCCTRL_SRTN (1 << 4) /* When SRTN =1, RTN3-0 value will be count */
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#define SSD1289_FCYCCTRL_SDIV (1 << 5) /* When SDIV = 1, DIV1-0 value will be count */
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#define SSD1289_FCYCCTRL_DIV_SHIFT (6) /* Set the division ratio of clocks */
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#define SSD1289_FCYCCTRL_DIV_MASK (3 << SSD1289_FCYCCTRL_DIV_SHIFT)
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# define SSD1289_FCYCCTRL_DIV1 (0 << SSD1289_FCYCCTRL_DIV_SHIFT)
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# define SSD1289_FCYCCTRL_DIV2 (1 << SSD1289_FCYCCTRL_DIV_SHIFT)
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# define SSD1289_FCYCCTRL_DIV4 (2 << SSD1289_FCYCCTRL_DIV_SHIFT)
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# define SSD1289_FCYCCTRL_DIV8 (3 << SSD1289_FCYCCTRL_DIV_SHIFT)
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#define SSD1289_FCYCCTRL_EQ_SHIFT (8) /* Sets the equalizing period */
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#define SSD1289_FCYCCTRL_EQ_MASK (3 << SSD1289_FCYCCTRL_EQ_SHIFT)
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# define SSD1289_FCYCCTRL_EQ(n) (((n)-1) << SSD1289_FCYCCTRL_EQ_SHIFT) /* n = 2-8 clocks */
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#define SSD1289_FCYCCTRL_SDT_SHIFT (12) /* Set delay amount from the gate output */
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#define SSD1289_FCYCCTRL_SDT_MASK (3 << SSD1289_FCYCCTRL_SDT_SHIFT)
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# define SSD1289_FCYCCTRL_SDT(n) ((n) << SSD1289_FCYCCTRL_SDT_SHIFT) /* n = 1-3 clocks */
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#define SSD1289_FCYCCTRL_NO_SHIFT (14) /* Sets amount of non-overlap of the gate output */
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#define SSD1289_FCYCCTRL_NO_MASK (3 << SSD1289_FCYCCTRL_NO_SHIFT)
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# define SSD1289_FCYCCTRL_NO(n) ((n) << SSD1289_FCYCCTRL_NO_SHIFT) /* n = 1-3 clocks */
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/* Power control 2 */
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#define SSD1289_PWRCTRL2_VRC_SHIFT (0) /* Adjust VCIX2 output voltage */
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#define SSD1289_PWRCTRL2_VRC_MASK (7 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p1V (0 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p2V (1 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p3V (2 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p4V (3 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p5V (4 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p6V (5 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p7V (6 << SSD1289_PWRCTRL2_VRC_SHIFT)
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# define SSD1289_PWRCTRL2_VRC_5p8V (7 << SSD1289_PWRCTRL2_VRC_SHIFT)
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/* Power control 3 */
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#define SSD1289_PWRCTRL3_VRH_SHIFT (0) /* Set amplitude magnification of VLCD63 */
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#define SSD1289_PWRCTRL3_VRH_MASK (15 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x1p540 (0 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x1p620 (1 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x1p700 (2 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x1p780 (3 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x1p850 (4 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x1p930 (5 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p020 (6 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p090 (7 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p165 (8 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p245 (9 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p335 (10 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p400 (11 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p500 (12 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p570 (13 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p645 (14 << SSD1289_PWRCTRL3_VRH_SHIFT)
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# define SSD1289_PWRCTRL3_VRH_x2p725 (15 << SSD1289_PWRCTRL3_VRH_SHIFT)
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/* Power control 4 */
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#define SSD1289_PWRCTRL4_VDV_SHIFT (8) /* Set amplitude magnification of VLCD63 */
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#define SSD1289_PWRCTRL4_VDV_MASK (32 << SSD1289_PWRCTRL4_VDV_SHIFT)
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# define SSD1289_PWRCTRL4_VDV(n) ((n) << SSD1289_PWRCTRL4_VDV_SHIFT)
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#define SSD1289_PWRCTRL4_VCOMG (1 << 13) /* VcomL variable */
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/* Gate scan start position */
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#define SSD1289_GSTART_MASK 0x1ff
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/* Sleep mode */
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#define SSD1289_SLEEP_ON (1 << 0)
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/* Entry mode */
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#define SSD1289_ENTRY_LG_SHIFT (0) /* Write after comparing */
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#define SSD1289_ENTRY_LG_MASK (7 << SSD1289_ENTRY_LG_SHIFT)
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#define SSD1289_ENTRY_AM (1 << 3) /* Address counter direction */
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#define SSD1289_ENTRY_ID_SHIFT (4) /* Address increment mode */
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#define SSD1289_ENTRY_ID_MASK (3 << SSD1289_ENTRY_ID_SHIFT)
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# define SSD1289_ENTRY_ID_HDECVDEC (0 << SSD1289_ENTRY_ID_SHIFT)
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# define SSD1289_ENTRY_ID_HINCVDEC (1 << SSD1289_ENTRY_ID_SHIFT)
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# define SSD1289_ENTRY_ID_HDECVINC (2 << SSD1289_ENTRY_ID_SHIFT)
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# define SSD1289_ENTRY_ID_HINCVINC (3 << SSD1289_ENTRY_ID_SHIFT)
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#define SSD1289_ENTRY_TY_SHIFT (6) /* RAM data write method */
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#define SSD1289_ENTRY_TY_MASK (3 << SSD1289_ENTRY_TY_SHIFT)
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# define SSD1289_ENTRY_TY_A (0 << SSD1289_ENTRY_TY_SHIFT)
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# define SSD1289_ENTRY_TY_B (1 << SSD1289_ENTRY_TY_SHIFT)
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# define SSD1289_ENTRY_TY_C (2 << SSD1289_ENTRY_TY_SHIFT)
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#define SSD1289_ENTRY_DMODE_SHIFT (8) /* Data display mode */
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#define SSD1289_ENTRY_DMODE_MASK (3 << SSD1289_ENTRY_DMODE_SHIFT)
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# define SSD1289_ENTRY_DMODE_RAM (0 << SSD1289_ENTRY_DMODE_SHIFT)
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# define SSD1289_ENTRY_DMODE_GENERIC (1 << SSD1289_ENTRY_DMODE_SHIFT)
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# define SSD1289_ENTRY_DMODE_RAMGEN (2 << SSD1289_ENTRY_DMODE_SHIFT)
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# define SSD1289_ENTRY_DMODE_GENRAM (3 << SSD1289_ENTRY_DMODE_SHIFT)
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#define SSD1289_ENTRY_WMODE (1 << 10) /* Select source of data in RAM */
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#define SSD1289_ENTRY_OEDEF (1 << 11) /* Define display window */
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#define SSD1289_ENTRY_TRANS (1 << 12) /* Transparent display */
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#define SSD1289_ENTRY_DFM_SHIFT (13) /* Color display mode */
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#define SSD1289_ENTRY_DFM_MASK (3 << SSD1289_ENTRY_DFM_SHIFT)
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# define SSD1289_ENTRY_DFM_262K (2 << SSD1289_ENTRY_DFM_SHIFT)
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# define SSD1289_ENTRY_DFM_65K (3 << SSD1289_ENTRY_DFM_SHIFT)
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#define SSD1289_ENTRY_VSMODE (1 << 15) /* Frame frequency depends on VSYNC */
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/* Generic Interface Control */
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#define SSD1289_GIFCTRL_INVVS (1 << 0) /* Sets the signal polarity of DOTCLK pin */
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#define SSD1289_GIFCTRL_INVHS (1 << 1) /* Sets the signal polarity of DEN pin */
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#define SSD1289_GIFCTRL_NVDEN (1 << 2) /* Sets the signal polarity of HSYNC pin */
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#define SSD1289_GIFCTRL_INVDOT (1 << 3) /* Sets the signal polarity of VSYNC pin */
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/* Horizontal Porch */
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#define SSD1289_HPORCH_HBP_SHIFT (0) /* Set delay from falling edge of HSYNC signal to data */
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#define SSD1289_HPORCH_HBP_MASK (0xff << SSD1289_HPORCH_HBP_SHIFT)
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#define SSD1289_HPORCH_XL_SHIFT (8) /* number of valid pixel per line */
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#define SSD1289_HPORCH_XL_MASK (0xff << SSD1289_HPORCH_XL_SHIFT)
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/* Vertical Porch */
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#define SSD1289_VPORCH_VBP_SHIFT (0) /* Set delay from falling edge of VSYNC signal to line */
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#define SSD1289_VPORCH_VBP_MASK (0xff << SSD1289_VPORCH_VBP_SHIFT)
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#define SSD1289_VPORCH_XFP_SHIFT (8) /* Delay from last line to falling edge of VSYNC of next frame */
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#define SSD1289_VPORCH_XFP_MASK (0xff << SSD1289_VPORCH_XFP_SHIFT)
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#define SSD1289_VPORCH_
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/* Power control 5 */
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#define SSD1289_PWRCTRL5_VCM_SHIFT (0) /* Set the VcomH voltage */
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#define SSD1289_PWRCTRL5_VCM_MASK (0x3f << SSD1289_PWRCTRL5_VCM_SHIFT)
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# define SSD1289_PWRCTRL5_VCM(n) ((n) << SSD1289_PWRCTRL5_VCM_SHIFT)
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#define SSD1289_PWRCTRL5_NOTP (1 << 7) /* 1=VCM valid */
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/* RAM write data mask 1 */
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#define SSD1289_WRMASK1_WMG_SHIFT (2)
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#define SSD1289_WRMASK1_WMG_MASK (0x3f << SSD1289_WRMASK1_WMG_SHIFT)
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#define SSD1289_WRMASK1_WMR_SHIFT (10)
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#define SSD1289_WRMASK1_WMR_MASK (0x3f << SSD1289_WRMASK1_WMR_SHIFT)
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#define SSD1289_WRMASK2_WMB_SHIFT (2)
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#define SSD1289_WRMASK2_WMB_MASK (0x3f << SSD1289_WRMASK2_WMB_SHIFT)
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/* Frame Frequency */
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#define SSD1289_FFREQ_OSC_SHIFT (12) /* Set the frame frequency */
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#define SSD1289_FFREQ_OSC_MASK (15 << SSD1289_FFREQ_OSC_SHIFT)
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# define SSD1289_FFREQ_OSC_FF50 (0 << SSD1289_FFREQ_OSC_SHIFT)
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# define SSD1289_FFREQ_OSC_FF55 (2 << SSD1289_FFREQ_OSC_SHIFT)
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# define SSD1289_FFREQ_OSC_FF60 (5 << SSD1289_FFREQ_OSC_SHIFT)
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# define SSD1289_FFREQ_OSC_FF65 (8 << SSD1289_FFREQ_OSC_SHIFT)
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# define SSD1289_FFREQ_OSC_FF70 (10 << SSD1289_FFREQ_OSC_SHIFT)
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# define SSD1289_FFREQ_OSC_FF75 (12 << SSD1289_FFREQ_OSC_SHIFT)
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# define SSD1289_FFREQ_OSC_FF80 (14 << SSD1289_FFREQ_OSC_SHIFT)
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/* VCOM OTP */
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#define SSD1289_VCOMOTP1_ACTIVATE 0x0006
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#define SSD1289_VCOMOTP1_FIRE 0x000a
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#define SSD1289_VCOMOTP2_ACTIVATE 0x80c0
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/* Optimize Access Speed 1, 2, 3 (omitted) */
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/* Gamma control 1-10. Magic values. I won't try to represent the fields. */
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/* Vertical scroll control 1 and 2 */
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#define SSD1289_VSCROLL_MASK 0x1ff /* Scroll length */
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/* Horizontal RAM address position */
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#define SSD1289_HADDR_HSA_SHIFT (0) /* Window horizontal start address */
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#define SSD1289_HADDR_HSA_MASK (0xff << SSD1289_HADDR_HSA_SHIFT)
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#define SSD1289_HADDR_HEA_SHIFT (8) /* Window horizontal end address */
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#define SSD1289_HADDR_HEA_MASK (0xff << SSD1289_HADDR_HEA_SHIFT)
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/* Vertical RAM address start/end position */
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#define SSD1289_VSTART_MASK 0x1ff /* Window Vertical start address */
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#define SSD1289_VEND_MASK 0x1ff /* Window Vertical end address */
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/* First window start/end */
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#define SSD1289_W1START_MASK 0x1ff /* Start line for first screen */
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#define SSD1289_W1END_MASK 0x1ff /* End line for first screen */
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/* Second window start/end */
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#define SSD1289_W2START_MASK 0x1ff /* Start line for second screen */
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#define SSD1289_W2END_MASK 0x1ff /* End line for second screen */
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/* Set GDDRAM X/Y address counter */
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#define SSD1289_XADDR_MASK 0xff /* GDDRAM X address in the address counter */
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#define SSD1289_YADDR_MASK 0x1ff /* GDDRAM Y address in the address counter */
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#endif /* CONFIG_LCD_SSD1289 */
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#endif /* __DRIVERS_LCD_SSD1289_H */
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