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nuttx/configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h
Gregory Nutt 2fc0fbcf7e Squashed commit of the following: 
commit 89e9d426e91c056e659fccf5e5c4392618f8f777
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Mon Jul 24 16:44:19 2017 -0600

    Update some comments

commit 9c5d8a5833350006ed389e898b11c8c8a20e5f4f
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Mon Jul 24 16:15:54 2017 -0600

    Spirit:  Rename drivers/wireless/spirit/src to lib.  Move Spirit network driver out of IEEE802.15.4 into drivers/wireless/spirit/drivers

commit cabc0ec9e6eb558dcb715ab17264383aa0105e7a
Merge: 87b616414a 6bd744c4b3
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Mon Jul 24 15:38:40 2017 -0600

    Merge remote-tracking branch 'origin/master' into spirit

commit 87b616414a79c01a71acea78f8258e05325c1996
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Mon Jul 24 15:37:27 2017 -0600

    Spirit radio driver is mutating into a standalone network driver.

commit 507798233868a661ae8adad3e3aa117075a7a146
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Mon Jul 24 13:32:08 2017 -0600

    Spirit: More radio initialization logic

commit 33af25704ce9ca83d576300d153cfe31cc6d2576
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Mon Jul 24 12:19:14 2017 -0600

    Spirit:  Beginning of radio initialization logic

commit 97b20014c016e55952a8f9d8f4ae29e2cc555b23
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Mon Jul 24 09:42:06 2017 -0600

    Spirit: More initialization logic.

commit 295d8e27824c0417fccea2344b30bb5c93ffbabe
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sun Jul 23 15:39:53 2017 -0600

    Spirit:  Add header file containing enumeration of commands.

commit 8a2d9dd8eb9cc70cbcdd1b913fc9022b9c9ec8da
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sun Jul 23 11:33:50 2017 -0600

    Spirit:  Add GPIO initialization logic

commit 8b6d80c44f92024c45a6ba63ba1af3fdafe94dc3
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sun Jul 23 10:07:25 2017 -0600

    Spirit:  Add interrupt control logic.

commit 423f846fe5c914f92a4bfea4d9d1fa33de1c77a5
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 19:06:52 2017 -0600

    Spirit: Yet a little more radio initialization logic.

commit 5895b979823e51ddde5ad52e6de66a8ad662e883
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 15:36:05 2017 -0600

    Spirit: A little more radio initialization logic.

commit 86311ab30aad386203c181c792847dd1d37f9a02
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 13:02:32 2017 -0600

    Spirit: A miniscule amount of radio initialization logic.

commit ad55e89d5ee12ea1eeea95fcd38ff3da0db4416a
Merge: 90a7666655 f4e46b0da7
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 10:56:30 2017 -0600

    Merge remote-tracking branch 'origin/master' into spirit

commit 90a766665534b05da0157dbc383cb06a98c86a79
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 10:52:52 2017 -0600

    Spirit1:  A few fixes for a clean build of initial configuration (not much there yet)

commit bbbf04c223230a52a7705a2161128265cfbaa480
Merge: 623d54a7f7 2319ea53a9
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 09:53:57 2017 -0600

    Merge remote-tracking branch 'origin/master' into spirit

commit 623d54a7f719e9032099f88f38203efee4b80722
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 09:43:52 2017 -0600

    b-l475e-iot01a: Add a configuration for testing sprit radio.

commit d309d73d9f4665f9d870eb03531f450043d9389d
Merge: 52c3ddfae6 d88dc9b2e5
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 09:02:06 2017 -0600

    Merge remote-tracking branch 'origin/master' into spirit

commit 52c3ddfae6802e111c2b5cf1207baf21a61dd00b
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Sat Jul 22 08:33:04 2017 -0600

    Spirit:  Add register definition header file.

commit 8d842ab5e8f9ca653b42f9ee88dc279f06b4fa98
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Fri Jul 21 17:27:03 2017 -0600

    b-l475e-iot01a: Add initial, unverified support for the SPSRGF/Spirit1 module.

commit 73d902a1048616fb9c2dd2147cabcd8ee78e19ac
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Fri Jul 21 15:49:43 2017 -0600

    Spirit: Fixes to get skeleton IEEE 802.15.4 driver build.

commit ebc5a8387bb94f0cc3827533795f3e4a33207e67
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Fri Jul 21 15:16:29 2017 -0600

    Spirit1:  Add framework for IEEE 802.15.4 driver.  Does not yet build.

commit 52e195a7ae14ddb18bdd56258f4877381d2501ca
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Fri Jul 21 14:02:42 2017 -0600

    Spirit:  A little more SPI logic.

commit 90048d0c5b8a5af4d81a15d99535c84ed38d8ae9
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Fri Jul 21 11:19:06 2017 -0600

    Spirit: Build directories setup.  Some initial files added, mostly just to verify build.

commit 8273a381ac1f6bb081b292b5e73226185e9e634c
Author: Gregory Nutt <gnutt@nuttx.org>
Date:   Fri Jul 21 08:34:04 2017 -0600

    USB composite:  Remove references to CDC/ACM and USB MSC from composite logic.  They are no longer coupled.
2017-07-24 16:46:30 -06:00

396 lines
14 KiB
C
Raw Blame History

/************************************************************************************
* configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIGS_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H
#define __CONFIGS_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocking *************************************************************************/
/* The stm32l476vg-disco supports both HSE and LSE crystals. As shipped, the HSE
* crystal is not populated. Therefore the stm32l476vg-disco will need to run off the
* 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
*/
/* HSI - 16 MHz RC factory-trimmed
* LSI - 32 KHz RC
* MSI - variable up to 48 MHz, synchronized to LSE
* HSE - not installed
* LSE - 32.768 kHz installed
*/
#define STM32L4_HSI_FREQUENCY 16000000ul
#define STM32L4_LSI_FREQUENCY 32000
#define STM32L4_LSE_FREQUENCY 32768
#define BOARD_AHB_FREQUENCY 80000000ul
/* XXX there needs to be independent selections for the System Clock Mux and
* the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
* Source Mux is chosen by the following define. This is probably OK in many
* cases, but should be separated to support other power configurations.
*/
#if 0
# define HSI_CLOCK_CONFIG 1 /* HSI-16 clock configuration */
#elif 0
/* Make sure you actually installed one! */
# define HSE_CLOCK_CONFIG 1 /* HSE with 8 MHz xtal */
#else
# define MSI_CLOCK_CONFIG 1 /* MSI @ 4 MHz autotrimmed via LSE */
#endif
#if defined(HSI_CLOCK_CONFIG)
#define STM32L4_BOARD_USEHSI 1
/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
as per comment above HSI) */
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
/* 'main' PLL config; we use this to generate our system clock via the R
* output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
*
* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
* the system clock; this should be configurable since not all applications may
* want things done this way.
*/
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
#define STM32L4_PLLCFG_PLLP 0
#undef STM32L4_PLLCFG_PLLP_ENABLED
#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
#define STM32L4_PLLCFG_PLLQ_ENABLED
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
#define STM32L4_PLLCFG_PLLR_ENABLED
/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
* do that with the main PLL's N value. We set N = 13, and enable
* the Q output (ultimately for CLK48) with /4. So,
* 16 MHz / 1 * 12 / 4 = 48 MHz
*
* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
* menuconfig, or else all this is a moot point, and the various 48 MHz
* peripherals will not work (RNG at present). I would suggest removing
* that option from Kconfig altogether, and simply making it an option
* that is selected via a #define here, like all these other params.
*/
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
#define STM32L4_PLLSAI1CFG_PLLP 0
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLR 0
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
/* 'SAIPLL2' is not used in this application */
#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
#define STM32L4_PLLSAI2CFG_PLLP 0
#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
#define STM32L4_PLLSAI2CFG_PLLR 0
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
#define STM32L4_USE_LSE 1
/* AHB clock (HCLK) is SYSCLK (80MHz) */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
/* Timers driven from APB1 will be twice PCLK1 */
/* REVISIT : this can be configured */
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (80MHz) */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
/* Timers driven from APB2 will be twice PCLK2 */
/* REVISIT : this can be configured */
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1
*/
/* REVISIT : this can be configured */
#elif defined(HSE_CLOCK_CONFIG)
/* Use the HSE */
#define STM32L4_BOARD_USEHSE 1
/* XXX sysclk mux = pllclk */
/* XXX pll source mux = hse */
/* Prescaler common to all PLL inputs */
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
/* 'main' PLL config; we use this to generate our system clock */
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20)
#define STM32L4_PLLCFG_PLLP 0
#undef STM32L4_PLLCFG_PLLP_ENABLED
#define STM32L4_PLLCFG_PLLQ 0
#undef STM32L4_PLLCFG_PLLQ_ENABLED
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
#define STM32L4_PLLCFG_PLLR_ENABLED
/* 'SAIPLL1' is used to generate the 48 MHz clock */
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
#define STM32L4_PLLSAI1CFG_PLLP 0
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLR 0
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
/* 'SAIPLL2' is not used in this application */
#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
#define STM32L4_PLLSAI2CFG_PLLP 0
#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
#define STM32L4_PLLSAI2CFG_PLLR 0
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* Enable LSE (for the RTC) */
#define STM32L4_USE_LSE 1
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* Configure the APB1 prescaler */
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
/* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
#elif defined(MSI_CLOCK_CONFIG)
/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
#define STM32L4_BOARD_USEMSI 1
#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
/* XXX sysclk mux = pllclk */
/* XXX pll source mux = msi */
/* Prescaler common to all PLL inputs */
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
/* 'main' PLL config; we use this to generate our system clock */
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40)
#define STM32L4_PLLCFG_PLLP 0
#undef STM32L4_PLLCFG_PLLP_ENABLED
#define STM32L4_PLLCFG_PLLQ 0
#undef STM32L4_PLLCFG_PLLQ_ENABLED
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
#define STM32L4_PLLCFG_PLLR_ENABLED
/* 'SAIPLL1' is used to generate the 48 MHz clock */
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
#define STM32L4_PLLSAI1CFG_PLLP 0
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLR 0
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
/* 'SAIPLL2' is not used in this application */
#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
#define STM32L4_PLLSAI2CFG_PLLP 0
#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
#define STM32L4_PLLSAI2CFG_PLLR 0
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* Enable LSE (for the RTC) */
#define STM32L4_USE_LSE 1
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* Configure the APB1 prescaler */
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
/* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
#endif
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,8,15,16,17 are on APB2, others on APB1
*/
#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H */
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