408 lines
12 KiB
C
408 lines
12 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/nuc_irq.c
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* arch/arm/src/chip/nuc_irq.c
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*
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* Copyright (C) 2009-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "nvic.h"
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#include "up_arch.h"
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#include "os_internal.h"
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#include "up_internal.h"
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#include "nuc_irq.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Get a 32-bit version of the default priority */
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#define DEFPRIORITY32 \
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(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
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NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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volatile uint32_t *current_regs;
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nuc_dumpnvic
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*
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* Description:
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* Dump some interesting NVIC registers
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*
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****************************************************************************/
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#if defined(CONFIG_DEBUG_IRQ) && defined (CONFIG_DEBUG)
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static void nuc_dumpnvic(const char *msg, int irq)
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{
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irqstate_t flags;
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flags = irqsave();
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slldbg("NVIC (%s, irq=%d):\n", msg, irq);
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slldbg(" ISER: %08x ICER: %08x\n",
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getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
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slldbg(" ISPR: %08x ICPR: %08x\n",
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getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
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slldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
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getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
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getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
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slldbg(" %08x %08x %08x %08x\n",
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getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
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getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
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slldbg("SYSCON:\n");
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slldbg(" CPUID: %08x\n",
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getreg32(ARMV6M_SYSCON_CPUID));
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slldbg(" ICSR: %08x AIRCR: %08x\n",
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getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
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slldbg(" SCR: %08x CCR: %08x\n",
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getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
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slldbg(" SHPR2: %08x SHPR3: %08x\n",
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getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
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irqrestore(flags);
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}
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#else
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# define nuc_dumpnvic(msg, irq)
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#endif
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/****************************************************************************
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* Name: nuc_nmi, nuc_busfault, nuc_usagefault, nuc_pendsv,
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* nuc_dbgmonitor, nuc_pendsv, nuc_reserved
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*
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* Description:
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* Handlers for various execptions. None are handled and all are fatal
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* error conditions. The only advantage these provided over the default
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* unexpected interrupt handler is that they provide a diagnostic output.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG
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static int nuc_nmi(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! NMI received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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static int nuc_pendsv(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! PendSV received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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static int nuc_reserved(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! Reserved interrupt\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: nuc_clrpend
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*
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* Description:
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* Clear a pending interrupt at the NVIC.
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*
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****************************************************************************/
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static inline void nuc_clrpend(int irq)
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{
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/* This will be called on each interrupt exit whether the interrupt can be
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* enambled or not. So this assertion is necessarily lame.
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*/
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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/* Check for an external interrupt */
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if (irq >= NUC_IRQ_INTERRUPT && irq < NUC_IRQ_INTERRUPT + 32)
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{
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/* Set the appropriate bit in the ISER register to enable the
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* interrupt
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*/
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putreg32((1 << (irq - NUC_IRQ_INTERRUPT)), ARMV6M_NVIC_ICPR);
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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****************************************************************************/
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void up_irqinitialize(void)
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{
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uint32_t regaddr;
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int i;
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/* Disable all interrupts */
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putreg32(0xffffffff, ARMV6M_NVIC_ICER);
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/* Set all interrupts (and exceptions) to the default priority */
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putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2);
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putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3);
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/* Now set all of the interrupt lines to the default priority */
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for (i = 0; i < 8; i++)
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{
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regaddr = ARMV6M_NVIC_IPR(i);
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putreg32(DEFPRIORITY32, regaddr);
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}
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/* currents_regs is non-NULL only while processing an interrupt */
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current_regs = NULL;
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/* Attach the SVCall and Hard Fault exception handlers. The SVCall
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* exception is used for performing context switches; The Hard Fault
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* must also be caught because a SVCall may show up as a Hard Fault
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* under certain conditions.
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*/
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irq_attach(NUC_IRQ_SVCALL, up_svcall);
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irq_attach(NUC_IRQ_HARDFAULT, up_hardfault);
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/* Attach all other processor exceptions (except reset and sys tick) */
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#ifdef CONFIG_DEBUG
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irq_attach(NUC_IRQ_NMI, nuc_nmi);
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irq_attach(NUC_IRQ_PENDSV, nuc_pendsv);
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irq_attach(NUC_IRQ_RESERVED, nuc_reserved);
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#endif
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nuc_dumpnvic("initial", NR_IRQS);
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* And finally, enable interrupts */
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irqenable();
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#endif
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_disable_irq(int irq)
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{
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/* This will be called on each interrupt (via up_maskack_irq()) whether
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* the interrupt can be disabled or not. So this assertion is necessarily
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* lame.
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*/
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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/* Check for an external interrupt */
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if (irq >= NUC_IRQ_INTERRUPT && irq < NUC_IRQ_INTERRUPT + 32)
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{
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/* Set the appropriate bit in the ICER register to disable the
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* interrupt
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*/
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putreg32((1 << (irq - NUC_IRQ_INTERRUPT)), ARMV6M_NVIC_ICER);
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}
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/* Handle processor exceptions. Only SysTick can be disabled */
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else if (irq == NUC_IRQ_SYSTICK)
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{
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modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
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}
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nuc_dumpnvic("disable", irq);
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Enable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_enable_irq(int irq)
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{
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/* This will be called on each interrupt exit whether the interrupt can be
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* enambled or not. So this assertion is necessarily lame.
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*/
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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/* Check for external interrupt */
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if (irq >= NUC_IRQ_INTERRUPT && irq < NUC_IRQ_INTERRUPT + 32)
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{
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/* Set the appropriate bit in the ISER register to enable the
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* interrupt
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*/
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putreg32((1 << (irq - NUC_IRQ_INTERRUPT)), ARMV6M_NVIC_ISER);
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}
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/* Handle processor exceptions. Only SysTick can be disabled */
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else if (irq == NUC_IRQ_SYSTICK)
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{
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modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE);
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}
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nuc_dumpnvic("enable", irq);
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}
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/****************************************************************************
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* Name: up_maskack_irq
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*
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* Description:
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* Mask the IRQ and acknowledge it
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*
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****************************************************************************/
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void up_maskack_irq(int irq)
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{
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up_disable_irq(irq);
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nuc_clrpend(irq);
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}
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/****************************************************************************
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* Name: up_prioritize_irq
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*
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* Description:
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* Set the priority of an IRQ.
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*
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* Since this API is not supported on all architectures, it should be
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* avoided in common implementations where possible.
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_IRQPRIO
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int up_prioritize_irq(int irq, int priority)
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{
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uint32_t regaddr;
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uint32_t regval;
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int shift;
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DEBUGASSERT(irq == NUC_IRQ_SVCALL ||
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irq == NUC_IRQ_PENDSV ||
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irq == NUC_IRQ_SYSTICK ||
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(irq >= NUC_IRQ_INTERRUPT && irq < NR_IRQS));
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DEBUGASSERT(priority >= NVIC_SYSH_DISABLE_PRIORITY &&
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priority <= NVIC_SYSH_PRIORITY_MIN);
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/* Check for external interrupt */
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if (irq >= NUC_IRQ_INTERRUPT && irq < NUC_IRQ_INTERRUPT + 32)
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{
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/* ARMV6M_NVIC_IPR() maps register IPR0-IPR7 with four settings per
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* register.
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*/
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regaddr = ARMV6M_NVIC_IPR(irq >> 2);
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shift = (irq & 3) << 3;
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}
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/* Handle processor exceptions. Only SVCall, PendSV, and SysTick can be
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* reprioritized. And we will not permit modification of SVCall through
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* this function.
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*/
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else if (irq == NUC_IRQ_PENDSV)
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{
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regaddr = ARMV6M_SYSCON_SHPR2;
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shift = SYSCON_SHPR3_PRI_14_SHIFT;
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}
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else if (irq == NUC_IRQ_SYSTICK)
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{
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regaddr = ARMV6M_SYSCON_SHPR2;
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shift = SYSCON_SHPR3_PRI_15_SHIFT;
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}
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else
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{
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return ERROR;
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}
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/* Set the priority */
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regval = getreg32(regaddr);
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regval &= ~((uint32_t)0xff << shift);
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regval |= ((uint32_t)priority << shift);
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putreg32(regval, regaddr);
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nuc_dumpnvic("prioritize", irq);
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return OK;
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}
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#endif
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