2aa85fd17e
Summary The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all MCU-private functions begin with the name of the architecture, not up_. This PR addresses only these name changes for the ARM-private functions prototyped in arm_internal.h This change to the files only modifies the name of called functions. nxstyle fixes were made for all core architecture files. However, there are well over 5000 additional complaints from MCU drivers and board logic that are unrelated to to this change but were affected by the name change. It is not humanly possible to fix all of these. I ask that this change be treated like other cosmetic changes that we have done which do not require full nxstyle compliance. Impact There should be not impact of this change (other that one step toward more consistent naming). Testing stm32f4discovery:netnsh
214 lines
7.1 KiB
C
214 lines
7.1 KiB
C
/****************************************************************************
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* boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <debug.h>
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#include <nuttx/spi/spi.h>
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#include <nuttx/net/encx24j600.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "arm_arch.h"
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#include "arm_internal.h"
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#include "stm32_spi.h"
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#include "olimex-stm32-p107.h"
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#ifdef CONFIG_ENCX24J600
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* ENCX24J600
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*
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* --- ------ -------------- ------------------------------------------------
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* PIN NAME SIGNAL NOTES
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* --- ------ -------------- ------------------------------------------------
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*
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* 54 PB15 PB15-CS_UEXT ENCX24J600 #CS
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* 78 PC10 PC10-SPI3-SCK ENCX24J600 SCK
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* 79 PC11 PC11-SPI3-MISO ENCX24J600 MISO
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* 80 PC12 PC12-SPI3-MOSI ENCX24J600 MOSI
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* 95 PB8 PB8 ENCX24J600 #Interrupt
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*/
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/* ENCX24J600 is on SPI3 */
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#ifndef CONFIG_STM32_SPI3
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# error "Need CONFIG_STM32_SPI3 in the configuration"
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#endif
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#ifndef CONFIG_STM32_SPI3_REMAP
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# error "SPI should be remapped for UEXT use"
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#endif
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/* SPI Assumptions **********************************************************/
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#define ENCX24J600_SPI_PORTNO 3 /* On SPI1 */
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#define ENCX24J600_DEVNO 0 /* Only one ENCX24J600 */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct stm32_lower_s
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{
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const struct enc_lower_s lower; /* Low-level MCU interface */
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xcpt_t handler; /* ENCX24J600 interrupt handler */
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FAR void *arg; /* Argument that accompanies the handler */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static int up_attach(FAR const struct enc_lower_s *lower, xcpt_t handler,
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FAR void *arg);
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static void up_enable(FAR const struct enc_lower_s *lower);
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static void up_disable(FAR const struct enc_lower_s *lower);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* The ENCX24J600 normal provides interrupts to the MCU via a GPIO pin. The
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* following structure provides an MCU-independent mechanixm for controlling
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* the ENCX24J600 GPIO interrupt.
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*/
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static struct stm32_lower_s g_enclower =
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{
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.lower =
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{
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.attach = up_attach,
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.enable = up_enable,
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.disable = up_disable
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},
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.handler = NULL,
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.arg = NULL
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: struct enc_lower_s methods
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****************************************************************************/
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static int up_attach(FAR const struct enc_lower_s *lower, xcpt_t handler,
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FAR void *arg)
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{
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FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower;
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/* Just save the handler for use when the interrupt is enabled */
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priv->handler = handler;
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priv->arg = arg;
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return OK;
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}
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static void up_enable(FAR const struct enc_lower_s *lower)
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{
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FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower;
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DEBUGASSERT(priv->handler != NULL);
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stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true,
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priv->handler, priv->arg);
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}
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/* REVISIT: Since the interrupt is torn down completely, any interrupts
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* the occur while "disabled" will be lost.
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*/
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static void up_disable(FAR const struct enc_lower_s *lower)
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{
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stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true,
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NULL, NULL);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_netinitialize
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****************************************************************************/
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void arm_netinitialize(void)
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{
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FAR struct spi_dev_s *spi;
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int ret;
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/* Assumptions:
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* 1) ENCX24J600 pins were configured in up_spi.c early in the boot-up phase.
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* 2) Clocking for the SPI1 peripheral was also provided earlier in boot-up.
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*/
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spi = stm32_spibus_initialize(ENCX24J600_SPI_PORTNO);
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if (!spi)
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{
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nerr("ERROR: Failed to initialize SPI port %d\n", ENCX24J600_SPI_PORTNO);
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return;
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}
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/* Bind the SPI port to the ENCX24J600 driver */
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ret = enc_initialize(spi, &g_enclower.lower, ENCX24J600_DEVNO);
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if (ret < 0)
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{
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nerr("ERROR: Failed to bind SPI port %d ENCX24J600 device %d: %d\n",
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ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO, ret);
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return;
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}
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ninfo("Bound SPI port %d to ENCX24J600 device %d\n",
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ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO);
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}
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#endif /* CONFIG_ENCX24J600 */
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