f0c29b34e5
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4882 42af7a65-404d-4744-a932-0658087f49c3
160 lines
7.6 KiB
C
160 lines
7.6 KiB
C
/************************************************************************************
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* arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define LPC43_EVNTRTR_HILO_OFFSET 0x0000 /* Level configuration register */
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#define LPC43_EVNTRTR_EDGE_OFFSET 0x0004 /* Edge configuration */
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#define LPC43_EVNTRTR_CLREN_OFFSET 0x0fd8 /* Clear event enable register */
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#define LPC43_EVNTRTR_SETEN_OFFSET 0x0fdc /* Set event enable register */
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#define LPC43_EVNTRTR_STATUS_OFFSET 0x0fe0 /* Event Status register */
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#define LPC43_EVNTRTR_ENABLE_OFFSET 0x0fe4 /* Event Enable register */
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#define LPC43_EVNTRTR_CLRSTAT_OFFSET 0x0fe8 /* Clear event status register */
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#define LPC43_EVNTRTR_SETSTAT_OFFSET 0x0fec /* Set event status register */
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/* Register Addresses ***************************************************************/
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#define LPC43_EVNTRTR_HILO (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_HILO_OFFSET)
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#define LPC43_EVNTRTR_EDGE (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_EDGE_OFFSET)
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#define LPC43_EVNTRTR_CLREN (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLREN_OFFSET)
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#define LPC43_EVNTRTR_SETEN (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETEN_OFFSET)
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#define LPC43_EVNTRTR_STATUS (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_STATUS_OFFSET)
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#define LPC43_EVNTRTR_ENABLE (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_ENABLE_OFFSET)
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#define LPC43_EVNTRTR_CLRSTAT (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLRSTAT_OFFSET)
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#define LPC43_EVNTRTR_SETSTAT (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETSTAT_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* Event router inputs. Bit settings common to all registers */
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#define EVNTRTR_SOURCE_WAKEUP0 0 /* WAKEUP0 pin */
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#define EVNTRTR_SOURCE_WAKEUP1 1 /* WAKEUP1 pin */
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#define EVNTRTR_SOURCE_WAKEUP2 2 /* WAKEUP2 pin */
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#define EVNTRTR_SOURCE_WAKEUP3 3 /* WAKEUP3 pin */
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#define EVNTRTR_SOURCE_ATIMER 4 /* Alarm timer interrupt */
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#define EVNTRTR_SOURCE_RTC 5 /* RTC interrupt and event recorder/monitor interrupt */
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#define EVNTRTR_SOURCE_BOD 6 /* BOD trip level 1interrupt */
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#define EVNTRTR_SOURCE_WWDT 7 /* WWDT interrupt */
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#define EVNTRTR_SOURCE_ETHERNET 8 /* Ethernet wake-up packet indicator */
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#define EVNTRTR_SOURCE_USB0 9 /* USB0 wake-up request signal */
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#define EVNTRTR_SOURCE_USB1 10 /* USB1 AHB_NEED_CLK signal */
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#define EVNTRTR_SOURCE_SDMMC 11 /* SD/MMC interrupt */
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#define EVNTRTR_SOURCE_CAN 12 /* C_CAN0 | C_CAN1 interrupt */
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#define EVNTRTR_SOURCE_TIM2 13 /* Combined timer output 2 (SCT output 2 | TIMER0 Ch2) */
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#define EVNTRTR_SOURCE_TIM6 14 /* Combined timer output 6 (SCT output 6 | TIMER1 Ch2) */
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#define EVNTRTR_SOURCE_QEI 15 /* QEI interrupt */
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#define EVNTRTR_SOURCE_TIM14 16 /* Combined timer output 14 (SCT output 14 | TIMER3 Ch2) */
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/* 17-18: Reserved */
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#define EVNTRTR_SOURCE_RESET 19 /* Reset event */
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#define EVNTRTR_WAKEUP0 (1 << EVNTRTR_SOURCE_WAKEUP0)
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#define EVNTRTR_WAKEUP1 (1 << EVNTRTR_SOURCE_WAKEUP1)
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#define EVNTRTR_WAKEUP2 (1 << EVNTRTR_SOURCE_WAKEUP2)
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#define EVNTRTR_WAKEUP3 (1 << EVNTRTR_SOURCE_WAKEUP3)
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#define EVNTRTR_ATIMER (1 << EVNTRTR_SOURCE_ATIMER)
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#define EVNTRTR_RTC (1 << EVNTRTR_SOURCE_RTC)
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#define EVNTRTR_BOD (1 << EVNTRTR_SOURCE_BOD)
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#define EVNTRTR_WWDT (1 << EVNTRTR_SOURCE_WWDT)
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#define EVNTRTR_ETH (1 << EVNTRTR_SOURCE_ETHERNET)
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#define EVNTRTR_USB0 (1 << EVNTRTR_SOURCE_USB0)
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#define EVNTRTR_USB1 (1 << EVNTRTR_SOURCE_USB1)
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#define EVNTRTR_SDMMC (1 << EVNTRTR_SOURCE_SDMMC)
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#define EVNTRTR_CAN (1 << EVNTRTR_SOURCE_CAN)
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#define EVNTRTR_TIM2 (1 << EVNTRTR_SOURCE_TIM2)
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#define EVNTRTR_TIM6 (1 << EVNTRTR_SOURCE_TIM6)
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#define EVNTRTR_QEI (1 << EVNTRTR_SOURCE_QEI)
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#define EVNTRTR_TIM14 (1 << EVNTRTR_SOURCE_TIM14)
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#define EVNTRTR_RESET (1 << EVNTRTR_SOURCE_RESET)
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/* Level configuration register */
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#define EVNTRTR_HILO(n) (1 << (n))
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/* Edge configuration */
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#define EVNTRTR_EDGE(n) (1 << (n))
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/* Clear event enable register */
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#define EVNTRTR_CLREN(n) (1 << (n))
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/* Set event enable register */
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#define EVNTRTR_SETEN(n) (1 << (n))
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/* Event Status register */
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#define EVNTRTR_STATUS(n) (1 << (n))
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/* Event Enable register */
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#define EVNTRTR_ENABLE(n) (1 << (n))
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/* Clear event status register */
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#define EVNTRTR_CLRSTAT(n) (1 << (n))
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/* Set event status register */
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#define EVNTRTR_SETSTAT(n) (1 << (n))
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H */
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