307 lines
10 KiB
C
307 lines
10 KiB
C
/****************************************************************************
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* arch/arm/src/sama5/sama5d2x_memorymap.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "mmu.h"
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#include "hardware/sam_memorymap.h"
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#include "sam_lcd.h"
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#include "sam_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* This table describes how to map a set of 1Mb pages to space the physical
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* address space of the SAMA5.
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*/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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const struct section_mapping_s g_section_mapping[] =
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{
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/* SAMA5 Internal Memories */
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are three ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. A second way is to map the use the AXI MATRIX remap register to
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* map physical address zero to the beginning of the text region,
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* either internal SRAM or EBI CS 0. Then we can set an identity
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* mapping to map the boot region at 0x0000:0000 to virtual address
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* 0x0000:00000. VBAR == 0x0000:0000.
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*
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* This method is used when booting from ISRAM or NOR FLASH. In
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* that case, vectors must lie at the beginning of NOFR FLASH.
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*
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* 3. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* This is the method used when booting from SDRAM.
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*
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* The system always boots from the ROM memory at address 0x0. After
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* reset, and until the Remap command is performed, the SRAM is accessible
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* at address 0x0020 0000. When the AXI Bus Matrix is remapped, the SRAM is
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* also available at address 0x0.
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*
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* If we are executing out of ISRAM, then the SAMA5 primary bootloader
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* probably copied us into ISRAM and set the AXI REMAP0 bit for us.
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*
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* If we are executing from external SDRAM, then a secondary bootloader
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* must have loaded us into SDRAM. In this case, simply set the VBAR
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* register to the address of the vector table (not necessary at the
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* beginning or SDRAM).
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*/
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#ifdef CONFIG_ARCH_LOWVECTORS
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{ SAM_SRAMREMAP_PSECTION, SAM_SRAMREMAP_VSECTION,
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SAM_SRAMREMAP_MMUFLAGS, SAM_SRAMREMAP_NSECTIONS
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},
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#endif
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{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
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SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
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},
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#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
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{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
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SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
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},
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#endif
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{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
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SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
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},
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{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
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SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
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},
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{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
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SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
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},
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{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
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SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
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},
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{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
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SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
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},
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#if defined(CONFIG_ARCH_CHIP_SAMA5D2) && defined(CONFIG_ARCH_L2CACHE)
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/* The SAMA5D2 features a second 128-Kbyte SRAM that can be allocated
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* either to the L2 cache controller or used as an internal SRAM. After
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* reset, this block is connected to the L2 cache controller. The
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* SRAM_SEL bit, located in the SFR_L2CC_HRAMC register, is used to
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* reassign this memory as system SRAM, making the two 128-Kbyte
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* RAMs contiguous.
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*/
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{ SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
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SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
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},
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#endif
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/* SAMA5 CS0 External Memories */
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#ifdef CONFIG_SAMA5_EBICS0
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{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
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SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
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},
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#endif
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/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
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* initialized. If we are running out of SDRAM now, we can assume that
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* some second level boot loader has properly configured SRAM for us.
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* In that case, we set the MMU flags for the final, fully cache-able
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* state.
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*
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* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
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* need not be repeated here.
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*
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* If we are running from ISRAM or NOR flash, then we will need to
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* configure the SDRAM ourselves. In this case, we set the MMU flags to
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* the strongly ordered, non-cacheable state. We need this direct access
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* to SDRAM in order to configure it. Once SDRAM has been initialized, it
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* will be re- configured in its final state.
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*/
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#ifdef NEED_SDRAM_MAPPING
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{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
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MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
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},
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{ SAM_DDRAESCS_PSECTION, SAM_DDRAESCS_VSECTION,
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MMU_STRONGLY_ORDERED, SAM_DDRAESCS_NSECTIONS
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},
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#endif
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/* SAMA5 CS1-3 External Memories */
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#ifdef CONFIG_SAMA5_EBICS1
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{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
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SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_EBICS2
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{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
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SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_EBICS3
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{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
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SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_QSPI0AES
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{ SAM_QSPI0AES_PSECTION, SAM_QSPI0AES_VSECTION,
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SAM_QSPI0AES_MMUFLAGS, SAM_QSPI0AES_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_QSPI1AES
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{ SAM_QSPI1AES_PSECTION, SAM_QSPI1AES_VSECTION,
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SAM_QSPI1AES_MMUFLAGS, SAM_QSPI1AES_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_SDMMC0
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{ SAM_SDMMC0_PSECTION, SAM_SDMMC0_VSECTION,
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SAM_SDMMC0_MMUFLAGS, SAM_SDMMC0_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_SDMMC1
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{ SAM_SDMMC1_PSECTION, SAM_SDMMC1_VSECTION,
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SAM_SDMMC1_MMUFLAGS, SAM_SDMMC1_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_HAVE_NAND
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{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
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SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_QSPI0
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{ SAM_QSPI0_PSECTION, SAM_QSPI0_VSECTION,
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SAM_QSPI0_MMUFLAGS, SAM_QSPI0_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_QSPI1
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{ SAM_QSPI1_PSECTION, SAM_QSPI1_VSECTION,
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SAM_QSPI1_MMUFLAGS, SAM_QSPI1_NSECTIONS
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},
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#endif
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/* SAMA5 Internal Peripherals
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*
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* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
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* There is nothing called SYSC in the SAMA5D4 memory map. The third
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* peripheral section is un-named in the SAMA5D4 memory map, but I have
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* chosen the name PERIPHC for this usage.
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*/
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{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
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SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
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},
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{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
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SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
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},
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{ SAM_PERIPHC_PSECTION, SAM_PERIPHC_VSECTION,
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SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS
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},
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/* LCDC Framebuffer. This entry reprograms a part of one of the above
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* regions, making it non-cacheable and non-buffereable.
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*
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* If SDRAM will be reconfigured, then we will defer setup of the
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* framebuffer until after the SDRAM remapping since the framebuffer
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* probablyresides in SDRAM.
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*/
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#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
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{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
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MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
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},
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#endif
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};
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/* The number of entries in the mapping table */
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#define NMAPPINGS \
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(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
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const size_t g_num_mappings = NMAPPINGS;
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
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* configured in a temporary state to support low-level ininitialization.
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* After the SDRAM has been fully initialized, this structure is used to
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* set the SDRM in its final, fully cache-able state.
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*/
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#ifdef NEED_SDRAM_REMAPPING
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const struct section_mapping_s g_operational_mapping[] =
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{
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/* This entry reprograms the SDRAM entry, making it cacheable and
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* bufferable.
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*/
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{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
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SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
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},
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{ SAM_DDRAESCS_PSECTION, SAM_DDRAESCS_VSECTION,
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SAM_DDRAESCS_MMUFLAGS, SAM_DDRAESCS_NSECTIONS
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},
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/* LCDC Framebuffer. This entry reprograms a part of one of the above
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* regions, making it non-cacheable and non-buffereable.
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*/
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#ifdef CONFIG_SAMA5_LCDC
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{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
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MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
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},
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#endif
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};
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/* The number of entries in the operational mapping table */
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#define NREMAPPINGS \
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(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
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const size_t g_num_opmappings = NREMAPPINGS;
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#endif /* NEED_SDRAM_REMAPPING */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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