87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/****************************************************************************
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* arch/arm/src/stm32f0l0g0/stm32_lse.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "arm_internal.h"
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#include "stm32_pwr.h"
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#include "stm32_rcc.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_rcc_enablelse
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*
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* Description:
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* Enable the External Low-Speed (LSE) oscillator.
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*
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* Todo:
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* Check for LSE good timeout and return with -1,
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*
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****************************************************************************/
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void stm32_rcc_enablelse(void)
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{
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/* The LSE is in the RTC domain and write access is denied to this domain
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* after reset, you have to enable write access using DBP bit in the PWR CR
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* register before to configuring the LSE.
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*/
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stm32_pwr_enablebkp(true);
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#if defined(CONFIG_ARCH_CHIP_STM32L0)
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/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
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* the RCC CSR register.
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*/
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modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON);
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/* Wait for the LSE clock to be ready */
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while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0)
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{
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}
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#elif defined(CONFIG_ARCH_CHIP_STM32F0)
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/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
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* the RCC BDCR register.
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*/
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
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/* Wait for the LSE clock to be ready */
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while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
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{
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}
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#endif
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/* Disable backup domain access if it was disabled on entry */
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stm32_pwr_enablebkp(false);
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}
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