ee84ea3875
Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt. Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
70 lines
2.6 KiB
C
70 lines
2.6 KiB
C
/****************************************************************************
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* arch/risc-v/include/litex/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_LITEX_IRQ_H
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#define __ARCH_RISCV_INCLUDE_LITEX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifdef CONFIG_LITEX_USE_CUSTOM_IRQ_DEFINITIONS
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#include CONFIG_LITEX_CUSTOM_IRQ_DEFINITIONS_PATH
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#else
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#include <arch/mode.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Map RISC-V exception code to NuttX IRQ */
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#define LITEX_IRQ_UART0 (RISCV_IRQ_EXT + 1)
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#define LITEX_IRQ_TIMER0 (RISCV_IRQ_EXT + 2)
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#define LITEX_IRQ_ETHMAC (RISCV_IRQ_EXT + 3)
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#define LITEX_IRQ_SDCARD (RISCV_IRQ_EXT + 4)
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#define LITEX_IRQ_GPIO_BASE (RISCV_IRQ_EXT + 5)
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#define LITEX_IRQ_GPIO_LENGTH 8
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/* The last hardware IRQ number */
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#define LITEX_LAST_IRQ (LITEX_IRQ_GPIO_BASE + LITEX_IRQ_GPIO_LENGTH)
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/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
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* as a second level of decoding: The first level dispatches to the GPIO
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* interrupt handler. The second to the decoded GPIO interrupt handler.
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*/
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#ifdef CONFIG_LITEX_GPIO_IRQ
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# define LITEX_NIRQ_GPIO LITEX_IRQ_GPIO_LENGTH * 32
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# define LITEX_FIRST_GPIOIRQ (LITEX_IRQ_LAST + 1)
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# define LITEX_LAST_GPIOIRQ (LITES_FIRST_GPIOIRQ + LITEX_NIRQ_GPIO)
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#else
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# define LITEX_NIRQ_GPIO 0
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#endif
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/* Total number of IRQs */
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#define NR_IRQS (LITEX_IRQ_LAST + LITEX_NIRQ_GPIO + 1)
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#endif /* CONFIG_LITEX_USE_CUSTOM_IRQ_DEFINITIONS */
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#endif /* __ARCH_RISCV_INCLUDE_LITEX_IRQ_H */
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