295 lines
7.7 KiB
C
295 lines
7.7 KiB
C
/****************************************************************************
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* arch/arm/src/nuc1xx/nuc_gpio.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <arch/nuc1xx/chip.h>
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#include "arm_internal.h"
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#include "chip.h"
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#include "hardware/nuc_gpio.h"
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#include "nuc_gpio.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nuc_configgpio
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin.
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* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
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* function, it must be unconfigured with nuc_unconfiggpio() with
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* the same cfgset first before it can be set to non-alternative function.
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*
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* Returned Value:
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* OK on success
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* ERROR on invalid port, or when pin is locked as ALT function.
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*
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****************************************************************************/
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int nuc_configgpio(gpio_cfgset_t cfgset)
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{
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uintptr_t base;
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uint32_t regaddr;
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uint32_t regval;
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uint32_t isrc;
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uint32_t imd;
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uint32_t ien;
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uint32_t value;
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int port;
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int pin;
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/* Decode the port and pin. Use the port number to get the GPIO base
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* address.
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*/
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port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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DEBUGASSERT((unsigned)port <= NUC_GPIO_PORTE);
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base = NUC_GPIO_CTRL_BASE(port);
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/* Set the GPIO PMD register */
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regaddr = base + NUC_GPIO_PMD_OFFSET;
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regval = getreg32(regaddr);
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regval &= ~GPIO_PMD_MASK(pin);
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switch (cfgset & GPIO_MODE_MASK)
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{
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default:
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case GPIO_INPUT: /* Input */
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value = GPIO_PMD_INPUT;
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break;
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case GPIO_OUTPUT: /* Push-pull output */
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value = GPIO_PMD_OUTPUT;
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break;
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case GPIO_OPENDRAIN: /* Open drain output */
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value = GPIO_PMD_OPENDRAIN;
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break;
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case GPIO_BIDI: /* Quasi bi-directional */
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value = GPIO_PMD_BIDI;
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break;
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}
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regval |= GPIO_PMD(pin, value);
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putreg32(regval, regaddr);
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/* Check if we need to disable the digital input path */
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regaddr = base + NUC_GPIO_OFFD_OFFSET;
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regval = getreg32(regaddr);
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regval &= ~GPIO_OFFD(pin);
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if ((cfgset & GPIO_ANALOG) != 0)
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{
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regval |= GPIO_OFFD(pin);
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}
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putreg32(regval, regaddr);
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/* Check if we need to enable debouncing */
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regaddr = base + NUC_GPIO_DBEN_OFFSET;
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regval = getreg32(regaddr);
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regval &= ~GPIO_DBEN(pin);
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if ((cfgset & GPIO_DEBOUNCE) != 0)
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{
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regval |= GPIO_DBEN(pin);
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}
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putreg32(regval, regaddr);
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/* Configure interrupting pins */
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isrc = getreg32(base + NUC_GPIO_ISRC_OFFSET);
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isrc &= ~GPIO_ISRC(pin);
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imd = getreg32(base + NUC_GPIO_IMD_OFFSET);
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imd &= ~GPIO_IMD(pin);
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ien = getreg32(base + NUC_GPIO_IEN_OFFSET);
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ien &= ~(GPIO_IF_EN(pin) | GPIO_IR_EN(pin));
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switch (cfgset & GPIO_INTERRUPT_MASK)
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{
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case GPIO_INTERRUPT_RISING_EDGE:
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isrc |= GPIO_ISRC(pin);
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ien |= GPIO_IR_EN(pin);
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break;
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case GPIO_INTERRUPT_FALLING_EDGE:
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isrc |= GPIO_ISRC(pin);
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ien |= GPIO_IF_EN(pin);
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break;
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case GPIO_INTERRUPT_BOTH_EDGES:
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isrc |= GPIO_ISRC(pin);
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ien |= (GPIO_IF_EN(pin) | GPIO_IR_EN(pin));
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break;
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case GPIO_INTERRUPT_HIGH_LEVEL:
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isrc |= GPIO_ISRC(pin);
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imd |= GPIO_IMD(pin);
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ien |= GPIO_IR_EN(pin);
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break;
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case GPIO_INTERRUPT_LOW_LEVEL:
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isrc |= GPIO_ISRC(pin);
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imd |= GPIO_IMD(pin);
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ien |= GPIO_IF_EN(pin);
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break;
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default:
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break;
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}
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putreg32(ien, base + NUC_GPIO_IEN_OFFSET);
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putreg32(imd, base + NUC_GPIO_IMD_OFFSET);
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putreg32(isrc, base + NUC_GPIO_ISRC_OFFSET);
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/* If the pin is an output, set the initial output value */
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if ((cfgset & GPIO_MODE_MASK) == GPIO_OUTPUT)
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{
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nuc_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
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}
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return 0;
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}
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/****************************************************************************
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* Name: nuc_gpiowrite
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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****************************************************************************/
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void nuc_gpiowrite(gpio_cfgset_t pinset, bool value)
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{
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#ifndef NUC_LOW
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irqstate_t flags;
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uintptr_t base;
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#endif
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int port;
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int pin;
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/* Decode the port and pin. Use the port number to get the GPIO base
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* address.
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*/
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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DEBUGASSERT((unsigned)port <= NUC_GPIO_PORTE);
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/* Only the low density NUC100/120 chips support bit-band access to GPIO
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* pins.
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*/
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#ifdef NUC_LOW
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putreg32((uint32_t)value, NUC_PORT_PDIO(port, pin));
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#else
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/* Get the base address of the GPIO port registers */
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base = NUC_GPIO_CTRL_BASE(port);
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/* Disable interrupts -- the following operations must be atomic */
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flags = enter_critical_section();
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/* Allow writing only to the selected pin in the DOUT register */
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putreg32(~(1 << pin), base + NUC_GPIO_DMASK_OFFSET);
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/* Set the pin to the selected value and re-enable interrupts */
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putreg32(((uint32_t)value << pin), base + NUC_GPIO_DOUT_OFFSET);
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leave_critical_section(flags);
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#endif
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}
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/****************************************************************************
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* Name: nuc_gpioread
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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****************************************************************************/
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bool nuc_gpioread(gpio_cfgset_t pinset)
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{
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#ifndef NUC_LOW
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uintptr_t base;
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#endif
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int port;
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int pin;
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/* Decode the port and pin. Use the port number to get the GPIO base
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* address.
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*/
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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DEBUGASSERT((unsigned)port <= NUC_GPIO_PORTE);
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/* Only the low density NUC100/120 chips support bit-band access to GPIO
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* pins.
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*/
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#ifdef NUC_LOW
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return (getreg32(NUC_PORT_PDIO(port, pin)) & PORT_MASK) != 0;
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#else
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/* Get the base address of the GPIO port registers */
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base = NUC_GPIO_CTRL_BASE(port);
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/* Return the state of the selected pin */
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return (getreg32(base + NUC_GPIO_PIN_OFFSET) & (1 << pin)) != 0;
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#endif
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}
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