545cfada38
If we are using the BASEPRI register to disable interrupts, then the answer is that we must disable ONLY the "normal interrupts". That is because we cannot disable SVCALL interrupts and we cannot permit SVCAll interrupts running at a higher priority than the high priority interrupts (otherwise, they will introduce jitter in the high priority interrupt response time.) Hence, if you need to disable the high priority interrupt, you will have to disable the interrupt either at the peripheral that generates the interrupt or at the NVIC. Disabling global interrupts via the BASEPRI register cannot effect high priority interrupts.
103 lines
5.1 KiB
C
103 lines
5.1 KiB
C
/*****************************************************************************
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* arch/arm/include/cxd56xx/chip.h
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*
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* Copyright 2018 Sony Semiconductor Solutions Corporation
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*
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* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CXD56M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
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#define CXD56M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define CXD56M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define CXD56M4_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
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#define NVIC_SYSH_PRIORITY_MIN CXD56M4_SYSH_PRIORITY_MIN
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#define NVIC_SYSH_PRIORITY_DEFAULT CXD56M4_SYSH_PRIORITY_DEFAULT
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#define NVIC_SYSH_PRIORITY_MAX CXD56M4_SYSH_PRIORITY_MAX
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#define NVIC_SYSH_PRIORITY_STEP CXD56M4_SYSH_PRIORITY_STEP
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/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
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* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
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* interrupts will not have execution priority. SVCall must have execution
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* priority in all cases.
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*
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* In the normal cases, interrupts are not nest-able and all interrupts run
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* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
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*
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* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
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* high priority interrupts are supported. These are not "nested" in the
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* normal sense of the word. These high priority interrupts can interrupt
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* normal processing but execute outside of OS (although they can "get back
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* into the game" via a PendSV interrupt).
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*
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* In the normal course of things, interrupts must occasionally be disabled
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* using the up_irq_save() inline function to prevent contention in use of
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* resources that may be shared between interrupt level and non-interrupt
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* level logic. Now the question arises, if we are using
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* CONFIG_ARCH_HIPRI_INTERRUPT=y, do we disable all interrupts except
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* SVCall (we cannot disable SVCall interrupts). Or do we only disable the
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* "normal" interrupts?
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*
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* If we are using the BASEPRI register to disable interrupts, then the
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* answer is that we must disable ONLY the "normal interrupts". That
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* is because we cannot disable SVCALL interrupts and we cannot permit
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* SVCAll interrupts running at a higher priority than the high priority
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* interrupts (otherwise, they will introduce jitter in the high priority
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* interrupt response time.)
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*
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* Hence, if you need to disable the high priority interrupt, you will have
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* to disable the interrupt either at the peripheral that generates the
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* interrupt or at the NVIC. Disabling global interrupts via the BASEPRI
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* register cannot effect high priority interrupts.
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*/
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/* The high priority interrupt must be highest priority. This prevents
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* SVCALL handling from adding jitter to high priority interrupt response.
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* Disabling interrupts will disable all interrupts EXCEPT SVCALL and the
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* high priority interrupts.
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*/
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#define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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#define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
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#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H */
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