908 lines
33 KiB
C
908 lines
33 KiB
C
/************************************************************************************
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* drivers/mtd/at45db.c
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* Driver for SPI-based AT45DB161D (16Mbit)
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*
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* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/* Ordering Code Detail:
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*
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* AT 45DB 16 1 D – SS U
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* | | | | | | `- Device grade
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* | | | | | `- Package Option
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* | | | | `- Device revision
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* | | | `- Interface: 1=serial
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* | | `- Capacity: 16=16Mbit
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* | `- Product family
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* `- Atmel designator
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*/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/arch.h>
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#include <nuttx/fs/ioctl.h>
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#include <nuttx/spi/spi.h>
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#include <nuttx/mtd/mtd.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* CONFIG_AT45DB_PREWAIT enables higher performance write logic: We leave the chip
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* busy after write and erase operations. This improves write and erase performance
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* because we do not have to wait as long between transactions (other processing can
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* occur while the chip is busy) but means that the chip must stay powered:
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*/
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#if defined(CONFIG_AT45DB_PWRSAVE) && defined(CONFIG_AT45DB_PREWAIT)
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# error "Both CONFIG_AT45DB_PWRSAVE and CONFIG_AT45DB_PREWAIT are defined"
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#endif
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/* If the user has provided no frequency, use 1MHz */
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#ifndef CONFIG_AT45DB_FREQUENCY
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# define CONFIG_AT45DB_FREQUENCY 1000000
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#endif
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/* SPI Commands *********************************************************************/
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/* Read commands */
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#define AT45DB_RDMN 0xd2 /* Main Memory Page Read */
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#define AT45DB_RDARRY 0xe8 /* Continuous Array Read (Legacy Command) */
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#define AT45DB_RDARRAYLF 0x03 /* Continuous Array Read (Low Frequency) */
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#define AT45DB_RDARRAYHF 0x0b /* Continuous Array Read (High Frequency) */
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#define AT45DB_RDBF1LF 0xd1 /* Buffer 1 Read (Low Frequency) */
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#define AT45DB_RDBF2LF 0xd3 /* Buffer 2 Read (Low Frequency) */
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#define AT45DB_RDBF1 0xd4 /* Buffer 1 Read */
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#define AT45DB_RDBF2 0xd6 /* Buffer 2 Read */
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/* Program and Erase Commands */
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#define AT45DB_WRBF1 0x84 /* Buffer 1 Write */
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#define AT45DB_WRBF2 0x87 /* Buffer 2 Write */
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#define AT45DB_BF1TOMNE 0x83 /* Buffer 1 to Main Memory Page Program with Built-in Erase */
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#define AT45DB_BF2TOMNE 0x86 /* Buffer 2 to Main Memory Page Program with Built-in Erase */
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#define AT45DB_BF1TOMN 0x88 /* Buffer 1 to Main Memory Page Program without Built-in Erase */
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#define AT45DB_BF2TOMN 0x89 /* Buffer 2 to Main Memory Page Program without Built-in Erase */
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#define AT45DB_PGERASE 0x81 /* Page Erase */
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#define AT45DB_BLKERASE 0x50 /* Block Erase */
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#define AT45DB_SECTERASE 0x7c /* Sector Erase */
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#define AT45DB_CHIPERASE1 0xc7 /* Chip Erase - byte 1 */
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# define AT45DB_CHIPERASE2 0x94 /* Chip Erase - byte 2 */
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# define AT45DB_CHIPERASE3 0x80 /* Chip Erase - byte 3 */
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# define AT45DB_CHIPERASE4 0x9a /* Chip Erase - byte 4 */
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#define AT45DB_MNTHRUBF1 0x82 /* Main Memory Page Program Through Buffer 1 */
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#define AT45DB_MNTHRUBF2 0x85 /* Main Memory Page Program Through Buffer 2 */
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/* Protection and Security Commands */
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#define AT45DB_ENABPROT1 0x3d /* Enable Sector Protection - byte 1 */
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# define AT45DB_ENABPROT2 0x2a /* Enable Sector Protection - byte 2 */
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# define AT45DB_ENABPROT3 0x7f /* Enable Sector Protection - byte 3 */
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# define AT45DB_ENABPROT4 0xa9 /* Enable Sector Protection - byte 4 */
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#define AT45DB_DISABPROT1 0x3d /* Disable Sector Protection - byte 1 */
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# define AT45DB_DISABPROT2 0x2a /* Disable Sector Protection - byte 2 */
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# define AT45DB_DISABPROT3 0x7f /* Disable Sector Protection - byte 3 */
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# define AT45DB_DISABPROT4 0x9a /* Disable Sector Protection - byte 4 */
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#define AT45DB_ERASEPROT1 0x3d /* Erase Sector Protection Register - byte 1 */
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# define AT45DB_ERASEPROT2 0x2a /* Erase Sector Protection Register - byte 2 */
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# define AT45DB_ERASEPROT3 0x7f /* Erase Sector Protection Register - byte 3 */
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# define AT45DB_ERASEPROT4 0xcf /* Erase Sector Protection Register - byte 4 */
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#define AT45DB_PROGPROT1 0x3d /* Program Sector Protection Register - byte 1 */
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# define AT45DB_PROGPROT2 0x2a /* Program Sector Protection Register - byte 2 */
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# define AT45DB_PROGPROT3 0x7f /* Program Sector Protection Register - byte 3 */
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# define AT45DB_PROGPROT4 0xfc /* Program Sector Protection Register - byte 4 */
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#define AT45DB_RDPROT 0x32 /* Read Sector Protection Register */
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#define AT45DB_LOCKDOWN1 0x3d /* Sector Lockdown - byte 1 */
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# define AT45DB_LOCKDOWN2 0x2a /* Sector Lockdown - byte 2 */
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# define AT45DB_LOCKDOWN3 0x7f /* Sector Lockdown - byte 3 */
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# define AT45DB_LOCKDOWN4 0x30 /* Sector Lockdown - byte 4 */
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#define AT45DB_RDLOCKDOWN 0x35 /* Read Sector Lockdown Register */
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#define AT45DB_PROGSEC1 0x9b /* Program Security Register - byte 1 */
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# define AT45DB_PROGSEC2 0x00 /* Program Security Register - byte 2 */
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# define AT45DB_PROGSEC3 0x00 /* Program Security Register - byte 3 */
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# define AT45DB_PROGSEC4 0x00 /* Program Security Register - byte 4 */
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#define AT45DB_RDSEC 0x77 /* Read Security Register */
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/* Additional commands */
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#define AT45DB_MNTOBF1XFR 0x53 /* Main Memory Page to Buffer 1 Transfer */
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#define AT45DB_MNTOBF2XFR 0x55 /* Main Memory Page to Buffer 2 Transfer */
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#define AT45DB_MNBF1CMP 0x60 /* Main Memory Page to Buffer 1 Compare */
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#define AT45DB_MNBF2CMP 0x61 /* Main Memory Page to Buffer 2 Compare */
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#define AT45DB_AUTOWRBF1 0x58 /* Auto Page Rewrite through Buffer 1 */
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#define AT45DB_AUTOWRBF2 0x59 /* Auto Page Rewrite through Buffer 2 */
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#define AT45DB_PWRDOWN 0xb9 /* Deep Power-down */
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#define AT45DB_RESUME 0xab /* Resume from Deep Power-down */
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#define AT45DB_RDSR 0xd7 /* Status Register Read */
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#define AT45DB_RDDEVID 0x9f /* Manufacturer and Device ID Read */
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#define AT45DB_MANUFACTURER 0x1f /* Manufacturer ID: Atmel */
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#define AT45DB_DEVID1_CAPMSK 0x1f /* Bits 0-4: Capacity */
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#define AT45DB_DEVID1_1MBIT 0x02 /* xxx0 0010 = 1Mbit AT45DB011 */
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#define AT45DB_DEVID1_2MBIT 0x03 /* xxx0 0012 = 2Mbit AT45DB021 */
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#define AT45DB_DEVID1_4MBIT 0x04 /* xxx0 0100 = 4Mbit AT45DB041 */
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#define AT45DB_DEVID1_8MBIT 0x05 /* xxx0 0101 = 8Mbit AT45DB081 */
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#define AT45DB_DEVID1_16MBIT 0x06 /* xxx0 0110 = 16Mbit AT45DB161 */
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#define AT45DB_DEVID1_32MBIT 0x07 /* xxx0 0111 = 32Mbit AT45DB321 */
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#define AT45DB_DEVID1_64MBIT 0x08 /* xxx0 1000 = 32Mbit AT45DB641 */
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#define AT45DB_DEVID1_FAMMSK 0xe0 /* Bits 5-7: Family */
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#define AT45DB_DEVID1_DFLASH 0x20 /* 001x xxxx = Dataflash */
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#define AT45DB_DEVID1_AT26DF 0x40 /* 010x xxxx = AT26DFxxx series (Not supported) */
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#define AT45DB_DEVID2_VERMSK 0x1f /* Bits 0-4: MLC mask */
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#define AT45DB_DEVID2_MLCMSK 0xe0 /* Bits 5-7: MLC mask */
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/* Status register bit definitions */
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#define AT45DB_SR_RDY (1 << 7) /* Bit 7: RDY/ Not BUSY */
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#define AT45DB_SR_COMP (1 << 6) /* Bit 6: COMP */
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#define AT45DB_SR_PROTECT (1 << 1) /* Bit 1: PROTECT */
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#define AT45DB_SR_PGSIZE (1 << 0) /* Bit 0: PAGE_SIZE */
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/* 1 Block = 16 pages; 1 sector = 256 pages */
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#define PG_PER_BLOCK (16)
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#define PG_PER_SECTOR (256)
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/************************************************************************************
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* Private Types
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************************************************************************************/
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/* This type represents the state of the MTD device. The struct mtd_dev_s
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* must appear at the beginning of the definition so that you can freely
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* cast between pointers to struct mtd_dev_s and struct at45db_dev_s.
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*/
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struct at45db_dev_s
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{
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struct mtd_dev_s mtd; /* MTD interface */
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FAR struct spi_dev_s *spi; /* Saved SPI interface instance */
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uint8_t pageshift; /* log2 of the page size (eg. 1 << 9 = 512) */
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uint32_t npages; /* Number of pages in the device */
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};
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/************************************************************************************
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* Private Function Prototypes
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************************************************************************************/
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/* Lock and per-transaction configuration */
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static void at45db_lock(struct at45db_dev_s *priv);
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static inline void at45db_unlock(struct at45db_dev_s *priv);
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/* Power management */
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#ifdef CONFIG_AT45DB_PWRSAVE
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static void at45db_pwrdown(struct at45db_dev_s *priv);
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static void at45db_resume(struct at45db_dev_s *priv);
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#else
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# define at45db_pwrdown(priv)
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# define at45db_resume(priv)
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#endif
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/* Low-level AT45DB Helpers */
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static inline int at45db_rdid(struct at45db_dev_s *priv);
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static inline uint8_t at45db_rdsr(struct at45db_dev_s *priv);
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static uint8_t at45db_waitbusy(struct at45db_dev_s *priv);
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static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t offset);
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static inline int at32db_chiperase(struct at45db_dev_s *priv);
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static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *buffer,
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off_t offset);
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/* MTD driver methods */
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static int at45db_erase(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks);
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static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock,
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size_t nblocks, FAR uint8_t *buf);
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static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock,
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size_t nblocks, FAR const uint8_t *buf);
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static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbytes,
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FAR uint8_t *buffer);
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static int at45db_ioctl(FAR struct mtd_dev_s *mtd, int cmd, unsigned long arg);
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/* Chip erase sequence */
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#define CHIP_ERASE_SIZE 4
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static const uint8_t g_chiperase[CHIP_ERASE_SIZE] = {0xc7, 0x94, 0x80, 0x9a};
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/* Sequence to program the device to binary page sizes{256, 512, 1024} */
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#define BINPGSIZE_SIZE 4
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static const uint8_t g_binpgsize[BINPGSIZE_SIZE] = {0x3d, 0x2a, 0x80, 0xa6};
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Name: at45db_lock
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************************************************************************************/
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static void at45db_lock(struct at45db_dev_s *priv)
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{
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/* On SPI busses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the busses for a sequence of
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* transfers. The bus should be locked before the chip is selected.
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*
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* This is a blocking call and will not return until we have exclusiv access to
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* the SPI buss. We will retain that exclusive access until the bus is unlocked.
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*/
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(void)SPI_LOCK(priv->spi, true);
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/* After locking the SPI bus, the we also need call the setfrequency, setbits, and
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* setmode methods to make sure that the SPI is properly configured for the device.
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* If the SPI buss is being shared, then it may have been left in an incompatible
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* state.
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*/
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SPI_SETMODE(priv->spi, SPIDEV_MODE0);
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SPI_SETBITS(priv->spi, 8);
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(void)SPI_SETFREQUENCY(priv->spi, CONFIG_AT45DB_FREQUENCY);
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}
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/************************************************************************************
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* Name: at45db_unlock
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************************************************************************************/
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static inline void at45db_unlock(struct at45db_dev_s *priv)
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{
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(void)SPI_LOCK(priv->spi, false);
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}
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/************************************************************************************
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* Name: at45db_pwrdown
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************************************************************************************/
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#ifdef CONFIG_AT45DB_PWRSAVE
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static void at45db_pwrdown(struct at45db_dev_s *priv)
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{
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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SPI_SEND(priv->spi, AT45DB_PWRDOWN);
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SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
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}
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#endif
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/************************************************************************************
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* Name: at45db_resume
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************************************************************************************/
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#ifdef CONFIG_AT45DB_PWRSAVE
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static void at45db_resume(struct at45db_dev_s *priv)
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{
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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SPI_SEND(priv->spi, AT45DB_RESUME);
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SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
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up_udelay(50);
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}
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#endif
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/************************************************************************************
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* Name: at45db_rdid
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************************************************************************************/
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static inline int at45db_rdid(struct at45db_dev_s *priv)
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{
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uint8_t capacity;
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uint8_t devid[3];
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fvdbg("priv: %p\n", priv);
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/* Configure the bus, and select this FLASH part. (The caller should alread have
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* loced the bus for exclusive access)
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*/
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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/* Send the " Manufacturer and Device ID Read" command and read the next three
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* ID bytes from the FLASH.
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*/
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(void)SPI_SEND(priv->spi, AT45DB_RDDEVID);
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SPI_RECVBLOCK(priv->spi, devid, 3);
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/* Deselect the FLASH */
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SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
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fvdbg("manufacturer: %02x devid1: %02x devid2: %02x\n",
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devid[0], devid[1], devid[2]);
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/* Check for a valid manufacturer and memory family */
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if (devid[0] == AT45DB_MANUFACTURER &&
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(devid[1] & AT45DB_DEVID1_FAMMSK) == AT45DB_DEVID1_DFLASH)
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{
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/* Okay.. is it a FLASH capacity that we understand? */
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capacity = devid[1] & AT45DB_DEVID1_CAPMSK;
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switch (capacity)
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{
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case AT45DB_DEVID1_1MBIT:
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/* Save the FLASH geometry for the 16Mbit AT45DB011 */
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priv->pageshift = 8; /* Page size = 256 bytes */
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priv->npages = 512; /* 512 pages */
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return OK;
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case AT45DB_DEVID1_2MBIT:
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/* Save the FLASH geometry for the 16Mbit AT45DB021 */
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priv->pageshift = 8; /* Page size = 256/264 bytes */
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priv->npages = 1024; /* 1024 pages */
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return OK;
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case AT45DB_DEVID1_4MBIT:
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/* Save the FLASH geometry for the 16Mbit AT45DB041 */
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priv->pageshift = 8; /* Page size = 256/264 bytes */
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priv->npages = 2048; /* 2048 pages */
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return OK;
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case AT45DB_DEVID1_8MBIT:
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/* Save the FLASH geometry for the 16Mbit AT45DB081 */
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priv->pageshift = 8; /* Page size = 256/264 bytes */
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priv->npages = 4096; /* 4096 pages */
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return OK;
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case AT45DB_DEVID1_16MBIT:
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/* Save the FLASH geometry for the 16Mbit AT45DB161 */
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priv->pageshift = 9; /* Page size = 512/528 bytes */
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priv->npages = 4096; /* 4096 pages */
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return OK;
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case AT45DB_DEVID1_32MBIT:
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/* Save the FLASH geometry for the 16Mbit AT45DB321 */
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priv->pageshift = 9; /* Page size = 512/528 bytes */
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priv->npages = 8192; /* 8192 pages */
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return OK;
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case AT45DB_DEVID1_64MBIT:
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/* Save the FLASH geometry for the 16Mbit AT45DB321 */
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priv->pageshift = 10; /* Page size = 1024/1056 bytes */
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priv->npages = 8192; /* 8192 pages */
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return OK;
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default:
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return -ENODEV;
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}
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}
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return -ENODEV;
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}
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/************************************************************************************
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* Name: at45db_rdsr
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************************************************************************************/
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static inline uint8_t at45db_rdsr(struct at45db_dev_s *priv)
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{
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uint8_t retval;
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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SPI_SEND(priv->spi, AT45DB_RDSR);
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retval = SPI_SEND(priv->spi, 0xff);
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||
return retval;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_waitbusy
|
||
************************************************************************************/
|
||
|
||
static uint8_t at45db_waitbusy(struct at45db_dev_s *priv)
|
||
{
|
||
uint8_t sr;
|
||
|
||
/* Poll the device, waiting for it to report that it is ready */
|
||
|
||
do
|
||
{
|
||
up_udelay(10);
|
||
sr = (uint8_t)at45db_rdsr(priv);
|
||
}
|
||
while ((sr & AT45DB_SR_RDY) == 0);
|
||
return sr;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_pgerase
|
||
************************************************************************************/
|
||
|
||
static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
|
||
{
|
||
uint8_t erasecmd[4];
|
||
off_t offset = sector << priv->pageshift;
|
||
|
||
fvdbg("sector: %08lx\n", (long)sector);
|
||
|
||
/* Higher performance write logic: We leave the chip busy after write and erase
|
||
* operations. This improves write and erase performance because we do not have
|
||
* to wait as long between transactions (other processing can occur while the chip
|
||
* is busy) but means that the chip must stay powered and that we must check if
|
||
* the chip is still busy on each entry point.
|
||
*/
|
||
|
||
#ifdef CONFIG_AT45DB_PREWAIT
|
||
at45db_waitbusy(priv);
|
||
#endif
|
||
|
||
/* "The Page Erase command can be used to individually erase any page in the main
|
||
* memory array allowing the Buffer to Main Memory Page Program to be utilized at a
|
||
* later time. ... To perform a page erase in the binary page size ..., the
|
||
* opcode 81H must be loaded into the device, followed by three address bytes
|
||
* ... When a low-to-high transition occurs on the CS pin, the part will erase the
|
||
* selected page (the erased state is a logical 1). ... the status register and the
|
||
* RDY/BUSY pin will indicate that the part is busy."
|
||
*/
|
||
|
||
erasecmd[0] = AT45DB_PGERASE; /* Page erase command */
|
||
erasecmd[1] = (offset >> 16) & 0xff; /* 24-bit offset MS bytes */
|
||
erasecmd[2] = (offset >> 8) & 0xff; /* 24-bit offset middle bytes */
|
||
erasecmd[3] = offset & 0xff; /* 24-bit offset LS bytes */
|
||
|
||
/* Erase the page */
|
||
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||
SPI_SNDBLOCK(priv->spi, erasecmd, 4);
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||
|
||
/* Wait for any erase to complete if we are not trying to improve write
|
||
* performance. (see comments above).
|
||
*/
|
||
|
||
#ifndef CONFIG_AT45DB_PREWAIT
|
||
at45db_waitbusy(priv);
|
||
#endif
|
||
fvdbg("Erased\n");
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at32db_chiperase
|
||
************************************************************************************/
|
||
|
||
static inline int at32db_chiperase(struct at45db_dev_s *priv)
|
||
{
|
||
fvdbg("priv: %p\n", priv);
|
||
|
||
/* Higher performance write logic: We leave the chip busy after write and erase
|
||
* operations. This improves write and erase performance because we do not have
|
||
* to wait as long between transactions (other processing can occur while the chip
|
||
* is busy) but means that the chip must stay powered and that we must check if
|
||
* the chip is still busy on each entry point.
|
||
*/
|
||
|
||
#ifdef CONFIG_AT45DB_PREWAIT
|
||
at45db_waitbusy(priv);
|
||
#endif
|
||
|
||
/* "The entire main memory can be erased at one time by using the Chip Erase
|
||
* command. To execute the Chip Erase command, a 4-byte command sequence C7H, 94H,
|
||
* 80H and 9AH must be clocked into the device. ... After the last bit of the opcode
|
||
* sequence has been clocked in, the CS pin can be deasserted to start the erase
|
||
* process. ... the Status Register will indicate that the device is busy. The Chip
|
||
* Erase command will not affect sectors that are protected or locked down...
|
||
*/
|
||
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||
SPI_SNDBLOCK(priv->spi, g_chiperase, CHIP_ERASE_SIZE);
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||
|
||
/* Wait for any erase to complete if we are not trying to improve write
|
||
* performance. (see comments above).
|
||
*/
|
||
|
||
#ifndef CONFIG_AT45DB_PREWAIT
|
||
at45db_waitbusy(priv);
|
||
#endif
|
||
return OK;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_pgwrite
|
||
************************************************************************************/
|
||
|
||
static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *buffer,
|
||
off_t page)
|
||
{
|
||
uint8_t wrcmd [4];
|
||
off_t offset = page << priv->pageshift;
|
||
|
||
fvdbg("page: %08lx offset: %08lx\n", (long)page, (long)offset);
|
||
|
||
/* We assume that sectors are not write protected */
|
||
|
||
wrcmd[0] = AT45DB_MNTHRUBF1; /* To main memory through buffer 1 */
|
||
wrcmd[1] = (offset >> 16) & 0xff; /* 24-bit address MS byte */
|
||
wrcmd[2] = (offset >> 8) & 0xff; /* 24-bit address middle byte */
|
||
wrcmd[3] = offset & 0xff; /* 24-bit address LS byte */
|
||
|
||
/* Higher performance write logic: We leave the chip busy after write and erase
|
||
* operations. This improves write and erase performance because we do not have
|
||
* to wait as long between transactions (other processing can occur while the chip
|
||
* is busy) but means that the chip must stay powered and that we must check if
|
||
* the chip is still busy on each entry point.
|
||
*/
|
||
|
||
#ifdef CONFIG_AT45DB_PREWAIT
|
||
at45db_waitbusy(priv);
|
||
#endif
|
||
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||
SPI_SNDBLOCK(priv->spi, wrcmd, 4);
|
||
SPI_SNDBLOCK(priv->spi, buffer, 1 << priv->pageshift);
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||
|
||
/* Wait for any erase to complete if we are not trying to improve write
|
||
* performance. (see comments above).
|
||
*/
|
||
|
||
#ifndef CONFIG_AT45DB_PREWAIT
|
||
at45db_waitbusy(priv);
|
||
#endif
|
||
fvdbg("Written\n");
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_erase
|
||
************************************************************************************/
|
||
|
||
static int at45db_erase(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks)
|
||
{
|
||
FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
|
||
size_t pgsleft = nblocks;
|
||
|
||
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
||
|
||
/* Take the lock so that we have exclusive access to the bus, then power up the
|
||
* FLASH device.
|
||
*/
|
||
|
||
at45db_lock(priv);
|
||
at45db_resume(priv);
|
||
|
||
/* Then erase each page */
|
||
|
||
while (pgsleft-- > 0)
|
||
{
|
||
/* Erase each sector */
|
||
|
||
at45db_pgerase(priv, startblock);
|
||
startblock++;
|
||
}
|
||
|
||
at45db_pwrdown(priv);
|
||
at45db_unlock(priv);
|
||
return (int)nblocks;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_bread
|
||
************************************************************************************/
|
||
|
||
static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks,
|
||
FAR uint8_t *buffer)
|
||
{
|
||
FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
|
||
ssize_t nbytes;
|
||
|
||
/* On this device, we can handle the block read just like the byte-oriented read */
|
||
|
||
nbytes = at45db_read(mtd, startblock << priv->pageshift, nblocks << priv->pageshift, buffer);
|
||
if (nbytes > 0)
|
||
{
|
||
return nbytes >> priv->pageshift;
|
||
}
|
||
return nbytes;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_bwrite
|
||
************************************************************************************/
|
||
|
||
static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks,
|
||
FAR const uint8_t *buffer)
|
||
{
|
||
FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
|
||
size_t pgsleft = nblocks;
|
||
|
||
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
||
|
||
/* Take the lock so that we have exclusive access to the bus, then power up the
|
||
* FLASH device.
|
||
*/
|
||
|
||
at45db_lock(priv);
|
||
at45db_resume(priv);
|
||
|
||
/* Write each page to FLASH */
|
||
|
||
while (pgsleft-- > 0)
|
||
{
|
||
at45db_pgwrite(priv, buffer, startblock);
|
||
startblock++;
|
||
}
|
||
|
||
at45db_pwrdown(priv);
|
||
at45db_unlock(priv);
|
||
|
||
return nblocks;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_read
|
||
************************************************************************************/
|
||
|
||
static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbytes,
|
||
FAR uint8_t *buffer)
|
||
{
|
||
FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
|
||
uint8_t rdcmd [5];
|
||
|
||
fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
|
||
|
||
/* Set up for the read */
|
||
|
||
rdcmd[0] = AT45DB_RDARRAYHF; /* FAST_READ is safe at all supported SPI speeds. */
|
||
rdcmd[1] = (offset >> 16) & 0xff; /* 24-bit address upper byte */
|
||
rdcmd[2] = (offset >> 8) & 0xff; /* 24-bit address middle byte */
|
||
rdcmd[3] = offset & 0xff; /* 24-bit address least significant byte */
|
||
rdcmd[4] = 0; /* Dummy byte */
|
||
|
||
/* Take the lock so that we have exclusive access to the bus, then power up the
|
||
* FLASH device.
|
||
*/
|
||
|
||
at45db_lock(priv);
|
||
at45db_resume(priv);
|
||
|
||
/* Higher performance write logic: We leave the chip busy after write and erase
|
||
* operations. This improves write and erase performance because we do not have
|
||
* to wait as long between transactions (other processing can occur while the chip
|
||
* is busy) but means that the chip must stay powered and that we must check if
|
||
* the chip is still busy on each entry point.
|
||
*/
|
||
|
||
#ifdef CONFIG_AT45DB_PREWAIT
|
||
at45db_waitbusy(priv);
|
||
#endif
|
||
|
||
/* Perform the read */
|
||
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||
SPI_SNDBLOCK(priv->spi, rdcmd, 5);
|
||
SPI_RECVBLOCK(priv->spi, buffer, nbytes);
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||
|
||
at45db_pwrdown(priv);
|
||
at45db_unlock(priv);
|
||
|
||
fvdbg("return nbytes: %d\n", (int)nbytes);
|
||
return nbytes;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_ioctl
|
||
************************************************************************************/
|
||
|
||
static int at45db_ioctl(FAR struct mtd_dev_s *mtd, int cmd, unsigned long arg)
|
||
{
|
||
FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
|
||
int ret = -EINVAL; /* Assume good command with bad parameters */
|
||
|
||
fvdbg("cmd: %d \n", cmd);
|
||
|
||
switch (cmd)
|
||
{
|
||
case MTDIOC_GEOMETRY:
|
||
{
|
||
FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg);
|
||
if (geo)
|
||
{
|
||
/* Populate the geometry structure with information need to know
|
||
* the capacity and how to access the device.
|
||
*
|
||
* NOTE: that the device is treated as though it where just an array
|
||
* of fixed size blocks. That is most likely not true, but the client
|
||
* will expect the device logic to do whatever is necessary to make it
|
||
* appear so.
|
||
*/
|
||
|
||
geo->blocksize = (1 << priv->pageshift);
|
||
geo->erasesize = geo->blocksize;
|
||
geo->neraseblocks = priv->npages;
|
||
ret = OK;
|
||
|
||
fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
|
||
geo->blocksize, geo->erasesize, geo->neraseblocks);
|
||
}
|
||
}
|
||
break;
|
||
|
||
case MTDIOC_BULKERASE:
|
||
{
|
||
/* Take the lock so that we have exclusive access to the bus, then
|
||
* power up the FLASH device.
|
||
*/
|
||
|
||
at45db_lock(priv);
|
||
at45db_resume(priv);
|
||
|
||
/* Erase the entire device */
|
||
|
||
ret = at32db_chiperase(priv);
|
||
at45db_pwrdown(priv);
|
||
at45db_unlock(priv);
|
||
}
|
||
break;
|
||
|
||
case MTDIOC_XIPBASE:
|
||
default:
|
||
ret = -ENOTTY; /* Bad command */
|
||
break;
|
||
}
|
||
|
||
fvdbg("return %d\n", ret);
|
||
return ret;
|
||
}
|
||
|
||
/************************************************************************************
|
||
* Public Functions
|
||
************************************************************************************/
|
||
|
||
/************************************************************************************
|
||
* Name: at45db_initialize
|
||
*
|
||
* Description:
|
||
* Create an initialize MTD device instance. MTD devices are not registered
|
||
* in the file system, but are created as instances that can be bound to
|
||
* other functions (such as a block or character driver front end).
|
||
*
|
||
************************************************************************************/
|
||
|
||
FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *spi)
|
||
{
|
||
FAR struct at45db_dev_s *priv;
|
||
uint8_t sr;
|
||
int ret;
|
||
|
||
fvdbg("spi: %p\n", spi);
|
||
|
||
/* Allocate a state structure (we allocate the structure instead of using
|
||
* a fixed, static allocation so that we can handle multiple FLASH devices.
|
||
* The current implementation would handle only one FLASH part per SPI
|
||
* device (only because of the SPIDEV_FLASH definition) and so would have
|
||
* to be extended to handle multiple FLASH parts on the same SPI bus.
|
||
*/
|
||
|
||
priv = (FAR struct at45db_dev_s *)kzalloc(sizeof(struct at45db_dev_s));
|
||
if (priv)
|
||
{
|
||
/* Initialize the allocated structure. (unsupported methods were
|
||
* nullified by kzalloc).
|
||
*/
|
||
|
||
priv->mtd.erase = at45db_erase;
|
||
priv->mtd.bread = at45db_bread;
|
||
priv->mtd.bwrite = at45db_bwrite;
|
||
priv->mtd.read = at45db_read;
|
||
priv->mtd.ioctl = at45db_ioctl;
|
||
priv->spi = spi;
|
||
|
||
/* Deselect the FLASH */
|
||
|
||
SPI_SELECT(spi, SPIDEV_FLASH, false);
|
||
|
||
/* Lock and configure the SPI bus. */
|
||
|
||
at45db_lock(priv);
|
||
at45db_resume(priv);
|
||
|
||
/* Identify the FLASH chip and get its capacity */
|
||
|
||
ret = at45db_rdid(priv);
|
||
if (ret != OK)
|
||
{
|
||
/* Unrecognized! Discard all of that work we just did and return NULL */
|
||
|
||
fdbg("Unrecognized\n");
|
||
goto errout;
|
||
}
|
||
|
||
/* Get the value of the status register (as soon as the device is ready) */
|
||
|
||
sr = at45db_waitbusy(priv);
|
||
|
||
/* Check if the device is configured as 256, 512 or 1024 bytes-per-page device */
|
||
|
||
if ((sr & AT45DB_SR_PGSIZE) == 0)
|
||
{
|
||
/* No, re-program it for the binary page size. NOTE: A power cycle
|
||
* is required after the device has be re-programmed.
|
||
*/
|
||
|
||
fdbg("Reprogramming page size\n");
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
|
||
SPI_SNDBLOCK(priv->spi, g_binpgsize, BINPGSIZE_SIZE);
|
||
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
|
||
goto errout;
|
||
}
|
||
|
||
/* Release the lock and power down the device */
|
||
|
||
at45db_pwrdown(priv);
|
||
at45db_unlock(priv);
|
||
}
|
||
|
||
/* Register the MTD with the procfs system if enabled */
|
||
|
||
#ifdef CONFIG_MTD_REGISTRATION
|
||
mtd_register(&priv->mtd, "at45db");
|
||
#endif
|
||
|
||
fvdbg("Return %p\n", priv);
|
||
return (FAR struct mtd_dev_s *)priv;
|
||
|
||
/* On any failure, we need free memory allocations and release the lock that
|
||
* we hold on the SPI bus. On failures, assume that we cannot talk to the
|
||
* device to do any more.
|
||
*/
|
||
|
||
errout:
|
||
at45db_unlock(priv);
|
||
kmm_free(priv);
|
||
return NULL;
|
||
}
|