0397fb1ed1
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1218 42af7a65-404d-4744-a932-0658087f49c3
230 lines
6.6 KiB
C
230 lines
6.6 KiB
C
/****************************************************************************
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* arch/arm/include/irq.h
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*
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* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_IRQ_H
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#define __ARCH_ARM_INCLUDE_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/irq.h>
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#include <arch/chip/irq.h>
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* IRQ Stack Frame Format:
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*
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* Context is always saved/restored in the same way:
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*
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* (1) stmia rx, {r0-r14}
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* (2) then the PC and CPSR
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*
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* This results in the following set of indices that
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* can be used to access individual registers in the
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* xcp.regs array:
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*/
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#define REG_R0 (0)
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#define REG_R1 (1)
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#define REG_R2 (2)
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#define REG_R3 (3)
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#define REG_R4 (4)
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#define REG_R5 (5)
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#define REG_R6 (6)
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#define REG_R7 (7)
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#define REG_R8 (8)
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#define REG_R9 (9)
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#define REG_R10 (10)
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#define REG_R11 (11)
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#define REG_R12 (12)
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#define REG_R13 (13)
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#define REG_R14 (14)
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#define REG_R15 (15)
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#define REG_CPSR (16)
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#define XCPTCONTEXT_REGS (17)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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#define REG_A1 REG_R0
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#define REG_A2 REG_R1
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#define REG_A3 REG_R2
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#define REG_A4 REG_R3
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#define REG_V1 REG_R4
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#define REG_V2 REG_R5
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#define REG_V3 REG_R6
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#define REG_V4 REG_R7
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#define REG_V5 REG_R8
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#define REG_V6 REG_R9
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#define REG_V7 REG_R10
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#define REG_SB REG_R9
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#define REG_SL REG_R10
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#define REG_FP REG_R11
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#define REG_IP REG_R12
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#define REG_SP REG_R13
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#define REG_LR REG_R14
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#define REG_PC REG_R15
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* This struct defines the way the registers are stored. We
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* need to save:
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*
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* 1 CPSR
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* 7 Static registers, v1-v7 (aka r4-r10)
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* 1 Frame pointer, fp (aka r11)
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* 1 Stack pointer, sp (aka r13)
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* 1 Return address, lr (aka r14)
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* ---
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* 11 (XCPTCONTEXT_USER_REG)
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*
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* On interrupts, we also need to save:
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* 4 Volatile registers, a1-a4 (aka r0-r3)
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* 1 Scratch Register, ip (aka r12)
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*---
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* 5 (XCPTCONTEXT_IRQ_REGS)
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*
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* For a total of 17 (XCPTCONTEXT_REGS)
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*/
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there
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* are pending signals to be processed.
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*/
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#ifndef CONFIG_DISABLE_SIGNALS
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of LR and CPSR used during
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* signal processing.
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*/
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uint32 saved_pc;
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uint32 saved_cpsr;
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#endif
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/* Register save area */
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uint32 regs[XCPTCONTEXT_REGS];
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* Save the current interrupt enable state & disable IRQs */
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static inline irqstate_t irqsave(void)
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{
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unsigned int flags;
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unsigned int temp;
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__asm__ __volatile__
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(
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"\tmrs %0, cpsr\n"
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"\torr %1, %0, #128\n"
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"\tmsr cpsr_c, %1"
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: "=r" (flags), "=r" (temp)
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:
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: "memory");
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return flags;
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}
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/* Restore saved IRQ & FIQ state */
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static inline void irqrestore(irqstate_t flags)
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{
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__asm__ __volatile__
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(
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"msr cpsr_c, %0"
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:
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: "r" (flags)
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: "memory");
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}
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static inline void system_call(swint_t func, int parm1,
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int parm2, int parm3)
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{
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__asm__ __volatile__
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(
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"mov\tr0,%0\n\t"
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"mov\tr1,%1\n\t"
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"mov\tr2,%2\n\t"
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"mov\tr3,%3\n\t"
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"swi\t0x900001\n\t"
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:
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: "r" ((long)(func)), "r" ((long)(parm1)),
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"r" ((long)(parm2)), "r" ((long)(parm3))
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: "r0", "r1", "r2", "r3", "lr");
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}
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#endif
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_IRQ_H */
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