c07d076bf5
Signed-off-by: chao an <anchao@xiaomi.com>
203 lines
6.1 KiB
C
203 lines
6.1 KiB
C
/****************************************************************************
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* arch/arm/include/arch.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/arch.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_ARCH_H
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#define __ARCH_ARM_INCLUDE_ARCH_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <nuttx/pgalloc.h>
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# include <nuttx/addrenv.h>
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#endif
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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#ifdef CONFIG_PIC
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/* This identifies the register the is used by the processor as the PIC base
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* register. It is usually r9 or r10
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*/
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#define PIC_REG r10
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#define PIC_REG_STRING "r10"
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/* Macros to get and set the PIC base register. picbase is assumed to be
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* of type (void*) and that it will fit into a uint32_t. These must be
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* inline so that they will be compatible with the ABIs rules for
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* preserving the PIC register
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*/
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#define up_getpicbase(ppicbase) \
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do { \
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uint32_t picbase; \
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__asm__ \
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( \
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"\tmov %0, " PIC_REG_STRING "\n\t" \
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: "=r"(picbase) \
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); \
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*ppicbase = (void *)picbase; \
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} while (0)
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#define up_setpicbase(picbase) \
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do { \
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uint32_t _picbase = (uint32_t)picbase; \
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__asm__ \
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( \
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"\tmov " PIC_REG_STRING ", %0\n\t" \
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: : "r"(_picbase) : PIC_REG_STRING \
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); \
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} while (0)
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#endif /* CONFIG_PIC */
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#ifdef CONFIG_ARCH_ADDRENV
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#if CONFIG_MM_PGSIZE != 4096
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# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
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#endif
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/* Convert 4KiB pages to 1MiB sections */
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# define __PG2SECT_SHIFT (20 - MM_PGSHIFT)
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# define __PG2SECT_MASK ((1 << __PG2SECT_SHIFT) - 1)
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# define ARCH_PG2SECT(p) (((p) + __PG2SECT_MASK) >> __PG2SECT_SHIFT)
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# define ARCH_SECT2PG(s) ((s) << __PG2SECT_SHIFT)
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# define ARCH_TEXT_NSECTS ARCH_PG2SECT(CONFIG_ARCH_TEXT_NPAGES)
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# define ARCH_DATA_NSECTS ARCH_PG2SECT(CONFIG_ARCH_DATA_NPAGES)
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# define ARCH_HEAP_NSECTS ARCH_PG2SECT(CONFIG_ARCH_HEAP_NPAGES)
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# ifdef CONFIG_MM_SHM
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# define ARCH_SHM_NSECTS ARCH_PG2SECT(ARCH_SHM_MAXPAGES)
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# endif
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# ifdef CONFIG_ARCH_STACK_DYNAMIC
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# define ARCH_STACK_NSECTS ARCH_PG2SECT(CONFIG_ARCH_STACK_NPAGES)
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# endif
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#endif /* CONFIG_ARCH_ADDRENV */
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/* Redefine the linker symbols as armlink style */
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#ifdef CONFIG_ARM_TOOLCHAIN_ARMCLANG
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# define _sinit Image$$init_section$$Base
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# define _einit Image$$init_section$$Limit
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifdef CONFIG_ARCH_ADDRENV
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/* The task group resources are retained in a single structure, task_group_s
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* that is defined in the header file nuttx/include/nuttx/sched.h. The type
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* group_addrenv_t must be defined by platform specific logic in
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* nuttx/arch/<architecture>/include/arch.h.
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*
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* These tables would hold the physical address of the level 2 page tables.
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* All would be initially NULL and would not be backed up with physical
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* memory until mappings in the level 2 page table are required.
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*/
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struct group_addrenv_s
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{
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/* Level 1 page table entries for each group section */
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uintptr_t *text[ARCH_TEXT_NSECTS];
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uintptr_t *data[ARCH_DATA_NSECTS];
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#ifdef CONFIG_BUILD_KERNEL
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uintptr_t *heap[ARCH_HEAP_NSECTS];
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#ifdef CONFIG_MM_SHM
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uintptr_t *shm[ARCH_SHM_NSECTS];
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#endif
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/* Initial heap allocation (in bytes). This exists only provide an
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* indirect path for passing the size of the initial heap to the heap
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* initialization logic. These operations are separated in time and
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* architecture. REVISIT: I would like a better way to do this.
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*/
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size_t heapsize;
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#endif
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};
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typedef struct group_addrenv_s group_addrenv_t;
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/* This type is used when the OS needs to temporarily instantiate a
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* different address environment. Used in the implementation of
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*
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* int up_addrenv_select(group_addrenv_t addrenv, save_addrenv_t *oldenv);
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* int up_addrenv_restore(save_addrenv_t oldenv);
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*
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* In this case, the saved valued in the L1 page table are returned
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*/
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struct save_addrenv_s
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{
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uint32_t text[ARCH_TEXT_NSECTS];
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uint32_t data[ARCH_DATA_NSECTS];
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#ifdef CONFIG_BUILD_KERNEL
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uint32_t heap[ARCH_HEAP_NSECTS];
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#ifdef CONFIG_MM_SHM
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uint32_t shm[ARCH_SHM_NSECTS];
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#endif
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#endif
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};
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typedef struct save_addrenv_s save_addrenv_t;
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARCH_ARM_INCLUDE_ARCH_H */
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