232 lines
8.5 KiB
C
232 lines
8.5 KiB
C
/****************************************************************************
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* arch/risc-v/src/bl602/hardware/bl602_common.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
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#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define BL602_FLASH_XIP_BASE 0x23000000
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#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
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#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
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#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024)
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#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
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#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024)
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#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
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#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024)
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#define BL602_WRAM_BASE 0x42020000
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#define BL602_WRAM_END (0x42020000 + 176 * 1024)
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#define BL602_WRAM_REMAP0_BASE 0x22020000
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#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024)
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#define BL602_WRAM_REMAP1_BASE 0x32020000
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#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024)
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#define BL602_WRAM_REMAP2_BASE 0x52020000
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#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024)
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#define BL602_TCM_BASE 0x22008000
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#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024)
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#define BL602_TCM_REMAP0_BASE 0x32008000
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#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024)
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#define BL602_TCM_REMAP1_BASE 0x42008000
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#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024)
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#define BL602_TCM_REMAP2_BASE 0x52008000
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#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024)
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/* BL602 peripherals base address */
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#define GLB_BASE ((uint32_t)0x40000000)
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#define RF_BASE ((uint32_t)0x40001000)
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/* AUX module base address */
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#define GPIP_BASE ((uint32_t)0x40002000)
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/* Security Debug module base address */
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#define SEC_DBG_BASE ((uint32_t)0x40003000)
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/* Security Engine module base address */
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#define SEC_ENG_BASE ((uint32_t)0x40004000)
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/* Trustzone control security base address */
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#define TZC_SEC_BASE ((uint32_t)0x40005000)
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/* Trustzone control none-security base address */
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#define TZC_NSEC_BASE ((uint32_t)0x40006000)
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#define EF_DATA_BASE ((uint32_t)0x40007000)
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#define EF_CTRL_BASE ((uint32_t)0x40007000)
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#define CCI_BASE ((uint32_t)0x40008000)
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/* L1 cache config base address */
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#define L1C_BASE ((uint32_t)0x40009000)
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#define UART0_BASE ((uint32_t)0x4000A000)
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#define UART1_BASE ((uint32_t)0x4000A100)
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#define SPI_BASE ((uint32_t)0x4000A200)
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#define I2C_BASE ((uint32_t)0x4000A300)
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#define PWM_BASE ((uint32_t)0x4000A400)
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#define TIMER_BASE ((uint32_t)0x4000A500)
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#define IR_BASE ((uint32_t)0x4000A600)
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#define SF_CTRL_BASE ((uint32_t)0x4000B000)
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#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
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#define DMA_BASE ((uint32_t)0x4000C000)
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#define SDU_BASE ((uint32_t)0x4000D000)
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/* Power down sleep module base address */
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#define PDS_BASE ((uint32_t)0x4000E000)
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/* Hibernate module base address */
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#define HBN_BASE ((uint32_t)0x4000F000)
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/* Always on module base address */
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#define AON_BASE ((uint32_t)0x4000F000)
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#define HBN_RAM_BASE ((uint32_t)0x40010000)
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#define BL_RD_WORD(addr) (*((volatile uint32_t *)(addr)))
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#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(addr)) = (val))
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#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(addr)))
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#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(addr)) = (val))
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#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(addr)))
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#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(addr)) = (val))
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#define BL_RDWD_FRM_BYTEP(p) \
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((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
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#define BL_WRWD_TO_BYTEP(p, val) \
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{ \
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p[0] = val & 0xff; \
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p[1] = (val >> 8) & 0xff; \
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p[2] = (val >> 16) & 0xff; \
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p[3] = (val >> 24) & 0xff; \
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}
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/**
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* @brief Register access macro
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*/
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#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)
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#define BL_WR_REG16(addr, regname, val) \
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BL_WR_SHORT(addr + regname##_OFFSET, val)
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#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET)
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#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)
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#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS))
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#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK)
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#define BL_GET_REG_BITS_VAL(val, bitname) \
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(((val)&bitname##_MSK) >> bitname##_POS)
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#define BL_SET_REG_BITS_VAL(val, bitname, bitval) \
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(((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
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#define BL_IS_REG_BIT_SET(val, bitname) \
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(((val) & (1U << (bitname##_POS))) != 0)
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#define __NOP() \
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__asm volatile("nop") /* This implementation generates debug information \
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*/
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#define BL_DRV_DUMMY \
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{ \
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__NOP(); \
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__NOP(); \
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__NOP(); \
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__NOP(); \
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}
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/* Std driver attribute macro */
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#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code")))
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#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const")))
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#define ATTR_TCM_SECTION __attribute__((section(".tcm_code")))
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#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const")))
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#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
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#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
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#define SystemCoreClockSet(val) BL_WR_WORD(0x4000f108, val)
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#define SystemCoreClockGet(val) BL_RD_WORD(0x4000f108)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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enum bl_ahb_slave1_e
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{
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BL_AHB_SLAVE1_GLB = 0x00,
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BL_AHB_SLAVE1_RF = 0x01,
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BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02,
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BL_AHB_SLAVE1_SEC_DBG = 0x03,
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BL_AHB_SLAVE1_SEC = 0x04,
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BL_AHB_SLAVE1_TZ1 = 0x05,
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BL_AHB_SLAVE1_TZ2 = 0x06,
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BL_AHB_SLAVE1_EFUSE = 0x07,
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BL_AHB_SLAVE1_CCI = 0x08,
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BL_AHB_SLAVE1_L1C = 0x09,
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BL_AHB_SLAVE1_RSVD0A = 0x0a,
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BL_AHB_SLAVE1_SFC = 0x0b,
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BL_AHB_SLAVE1_DMA = 0x0c,
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BL_AHB_SLAVE1_SDU = 0x0d,
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BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0e,
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BL_AHB_SLAVE1_RSVD0F = 0x0f,
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BL_AHB_SLAVE1_UART0 = 0x10,
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BL_AHB_SLAVE1_UART1 = 0x11,
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BL_AHB_SLAVE1_SPI = 0x12,
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BL_AHB_SLAVE1_I2C = 0x13,
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BL_AHB_SLAVE1_PWM = 0x14,
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BL_AHB_SLAVE1_TMR = 0x15,
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BL_AHB_SLAVE1_IRR = 0x16,
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BL_AHB_SLAVE1_CKS = 0x17,
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BL_AHB_SLAVE1_MAX = 0x18,
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H */
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