nuttx/arch/arm/include/armv7-m
2019-01-26 07:04:15 -06:00
..
irq_cmnvector.h Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
irq_lazyfpu.h Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
irq.h arch/arm/include/armv-7m/irq.h and armv6-m/irq.h: Remove redundant conditioning on CONFIG_BUILD_PROTECTED 2019-01-26 07:04:15 -06:00
nvicpri.h In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
spinlock.h i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. 2016-11-26 12:04:02 -06:00
syscall.h arch/arm: (1) Add semihost support for syslog, (2) Add semihost support for HostFS 2018-08-23 08:00:07 -06:00