899eb0b5ce
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4898 42af7a65-404d-4744-a932-0658087f49c3
372 lines
19 KiB
C
372 lines
19 KiB
C
/************************************************************************************
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* arch/arm/src/lpc43xx/lpc43_rtc.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
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#define __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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/* Miscellaneous registers */
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#define LPC43_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */
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#define LPC43_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */
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#define LPC43_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */
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#define LPC43_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */
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/* Consolidated time registers */
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#define LPC43_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */
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#define LPC43_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */
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#define LPC43_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */
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/* Time counter registers */
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#define LPC43_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */
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#define LPC43_RTC_MIN_OFFSET 0x0024 /* Minutes Register */
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#define LPC43_RTC_HOUR_OFFSET 0x0028 /* Hours Register */
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#define LPC43_RTC_DOM_OFFSET 0x002c /* Day of Month Register */
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#define LPC43_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */
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#define LPC43_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */
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#define LPC43_RTC_MONTH_OFFSET 0x0038 /* Months Register */
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#define LPC43_RTC_YEAR_OFFSET 0x003c /* Years Register */
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#define LPC43_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */
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/* Alarm register group */
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#define LPC43_RTC_ASEC_OFFSET 0x0060 /* Alarm value for Seconds */
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#define LPC43_RTC_AMIN_OFFSET 0x0064 /* Alarm value for Minutes */
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#define LPC43_RTC_AHOUR_OFFSET 0x0068 /* Alarm value for Hours */
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#define LPC43_RTC_ADOM_OFFSET 0x006c /* Alarm value for Day of Month */
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#define LPC43_RTC_ADOW_OFFSET 0x0070 /* Alarm value for Day of Week */
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#define LPC43_RTC_ADOY_OFFSET 0x0074 /* Alarm value for Day of Year */
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#define LPC43_RTC_AMON_OFFSET 0x0078 /* Alarm value for Months */
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#define LPC43_RTC_AYEAR_OFFSET 0x007c /* Alarm value for Year */
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/* General Purpose Registers.
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*
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* In addition to the RTC registers, 64 general purpose registers are available
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* to store data when the main power supply is switched off. The general purpose
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* registers reside in the RTC power domain and can be battery powered.
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*/
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#define LPC43_REGFILE_OFFSET(n) (0x0000 + ((n) << 2))
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#define LPC43_REGFILE0_OFFSET 0x0000
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#define LPC43_REGFILE1_OFFSET 0x0004
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#define LPC43_REGFILE2_OFFSET 0x0008
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#define LPC43_REGFILE3_OFFSET 0x000c
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#define LPC43_REGFILE4_OFFSET 0x0010
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#define LPC43_REGFILE5_OFFSET 0x0014
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#define LPC43_REGFILE6_OFFSET 0x0018
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#define LPC43_REGFILE7_OFFSET 0x001c
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#define LPC43_REGFILE8_OFFSET 0x0020
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#define LPC43_REGFILE9_OFFSET 0x0024
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#define LPC43_REGFILE10_OFFSET 0x0028
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#define LPC43_REGFILE11_OFFSET 0x002c
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#define LPC43_REGFILE12_OFFSET 0x0030
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#define LPC43_REGFILE13_OFFSET 0x0034
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#define LPC43_REGFILE14_OFFSET 0x0038
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#define LPC43_REGFILE15_OFFSET 0x003c
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#define LPC43_REGFILE16_OFFSET 0x0040
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#define LPC43_REGFILE17_OFFSET 0x0044
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#define LPC43_REGFILE18_OFFSET 0x0048
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#define LPC43_REGFILE19_OFFSET 0x004c
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#define LPC43_REGFILE20_OFFSET 0x0050
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#define LPC43_REGFILE21_OFFSET 0x0054
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#define LPC43_REGFILE22_OFFSET 0x0058
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#define LPC43_REGFILE23_OFFSET 0x005c
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#define LPC43_REGFILE24_OFFSET 0x0060
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#define LPC43_REGFILE25_OFFSET 0x0064
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#define LPC43_REGFILE26_OFFSET 0x0068
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#define LPC43_REGFILE27_OFFSET 0x006c
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#define LPC43_REGFILE28_OFFSET 0x0070
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#define LPC43_REGFILE29_OFFSET 0x0074
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#define LPC43_REGFILE30_OFFSET 0x0078
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#define LPC43_REGFILE31_OFFSET 0x007c
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#define LPC43_REGFILE32_OFFSET 0x0080
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#define LPC43_REGFILE33_OFFSET 0x0084
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#define LPC43_REGFILE34_OFFSET 0x0088
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#define LPC43_REGFILE35_OFFSET 0x008c
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#define LPC43_REGFILE36_OFFSET 0x0090
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#define LPC43_REGFILE37_OFFSET 0x0094
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#define LPC43_REGFILE38_OFFSET 0x0098
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#define LPC43_REGFILE39_OFFSET 0x009c
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#define LPC43_REGFILE40_OFFSET 0x00a0
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#define LPC43_REGFILE41_OFFSET 0x00a4
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#define LPC43_REGFILE42_OFFSET 0x00a8
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#define LPC43_REGFILE43_OFFSET 0x00ac
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#define LPC43_REGFILE44_OFFSET 0x00b0
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#define LPC43_REGFILE45_OFFSET 0x00b4
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#define LPC43_REGFILE46_OFFSET 0x00b8
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#define LPC43_REGFILE47_OFFSET 0x00bc
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#define LPC43_REGFILE48_OFFSET 0x00c0
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#define LPC43_REGFILE49_OFFSET 0x00c4
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#define LPC43_REGFILE50_OFFSET 0x00c8
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#define LPC43_REGFILE51_OFFSET 0x00cc
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#define LPC43_REGFILE52_OFFSET 0x00d0
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#define LPC43_REGFILE53_OFFSET 0x00d4
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#define LPC43_REGFILE54_OFFSET 0x00d8
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#define LPC43_REGFILE55_OFFSET 0x00dc
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#define LPC43_REGFILE56_OFFSET 0x00e0
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#define LPC43_REGFILE57_OFFSET 0x00e4
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#define LPC43_REGFILE58_OFFSET 0x00e8
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#define LPC43_REGFILE59_OFFSET 0x00ec
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#define LPC43_REGFILE60_OFFSET 0x00f0
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#define LPC43_REGFILE61_OFFSET 0x00f4
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#define LPC43_REGFILE62_OFFSET 0x00f8
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#define LPC43_REGFILE63_OFFSET 0x00fc
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/* Register addresses ***************************************************************/
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/* Miscellaneous registers */
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#define LPC43_RTC_ILR (LPC43_RTC_BASE+LPC43_RTC_ILR_OFFSET)
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#define LPC43_RTC_CCR (LPC43_RTC_BASE+LPC43_RTC_CCR_OFFSET)
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#define LPC43_RTC_CIIR (LPC43_RTC_BASE+LPC43_RTC_CIIR_OFFSET)
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#define LPC43_RTC_AMR (LPC43_RTC_BASE+LPC43_RTC_AMR_OFFSET)
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/* Consolidated time registers */
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#define LPC43_RTC_CTIME0 (LPC43_RTC_BASE+LPC43_RTC_CTIME0_OFFSET)
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#define LPC43_RTC_CTIME1 (LPC43_RTC_BASE+LPC43_RTC_CTIME1_OFFSET)
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#define LPC43_RTC_CTIME2 (LPC43_RTC_BASE+LPC43_RTC_CTIME2_OFFSET)
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/* Time counter registers */
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#define LPC43_RTC_SEC (LPC43_RTC_BASE+LPC43_RTC_SEC_OFFSET)
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#define LPC43_RTC_MIN (LPC43_RTC_BASE+LPC43_RTC_MIN_OFFSET)
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#define LPC43_RTC_HOUR (LPC43_RTC_BASE+LPC43_RTC_HOUR_OFFSET)
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#define LPC43_RTC_DOM (LPC43_RTC_BASE+LPC43_RTC_DOM_OFFSET)
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#define LPC43_RTC_DOW (LPC43_RTC_BASE+LPC43_RTC_DOW_OFFSET)
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#define LPC43_RTC_DOY (LPC43_RTC_BASE+LPC43_RTC_DOY_OFFSET)
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#define LPC43_RTC_MONTH (LPC43_RTC_BASE+LPC43_RTC_MONTH_OFFSET)
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#define LPC43_RTC_YEAR (LPC43_RTC_BASE+LPC43_RTC_YEAR_OFFSET)
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#define LPC43_RTC_CALIB (LPC43_RTC_BASE+LPC43_RTC_CALIB_OFFSET)
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/* Alarm register group */
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#define LPC43_RTC_ASEC (LPC43_RTC_BASE+LPC43_RTC_ASEC_OFFSET)
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#define LPC43_RTC_AMIN (LPC43_RTC_BASE+LPC43_RTC_AMIN_OFFSET)
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#define LPC43_RTC_AHOUR (LPC43_RTC_BASE+LPC43_RTC_AHOUR_OFFSET)
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#define LPC43_RTC_ADOM (LPC43_RTC_BASE+LPC43_RTC_ADOM_OFFSET)
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#define LPC43_RTC_ADOW (LPC43_RTC_BASE+LPC43_RTC_ADOW_OFFSET)
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#define LPC43_RTC_ADOY (LPC43_RTC_BASE+LPC43_RTC_ADOY_OFFSET)
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#define LPC43_RTC_AMON (LPC43_RTC_BASE+LPC43_RTC_AMON_OFFSET)
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#define LPC43_RTC_AYEAR (LPC43_RTC_BASE+LPC43_RTC_AYEAR_OFFSET)
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/* General Purpose Registers */
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#define LPC43_REGFILE(n) (LPC43_BACKUP_BASE+LPC43_REGFILE_OFFSET(n))
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#define LPC43_REGFILE0 (LPC43_BACKUP_BASE+LPC43_REGFILE0_OFFSET)
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#define LPC43_REGFILE1 (LPC43_BACKUP_BASE+LPC43_REGFILE1_OFFSET)
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#define LPC43_REGFILE2 (LPC43_BACKUP_BASE+LPC43_REGFILE2_OFFSET)
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#define LPC43_REGFILE3 (LPC43_BACKUP_BASE+LPC43_REGFILE3_OFFSET)
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#define LPC43_REGFILE4 (LPC43_BACKUP_BASE+LPC43_REGFILE4_OFFSET)
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#define LPC43_REGFILE5 (LPC43_BACKUP_BASE+LPC43_REGFILE5_OFFSET)
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#define LPC43_REGFILE6 (LPC43_BACKUP_BASE+LPC43_REGFILE6_OFFSET)
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#define LPC43_REGFILE7 (LPC43_BACKUP_BASE+LPC43_REGFILE7_OFFSET)
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#define LPC43_REGFILE8 (LPC43_BACKUP_BASE+LPC43_REGFILE8_OFFSET)
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#define LPC43_REGFILE9 (LPC43_BACKUP_BASE+LPC43_REGFILE9_OFFSET)
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#define LPC43_REGFILE10 (LPC43_BACKUP_BASE+LPC43_REGFILE10_OFFSET)
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#define LPC43_REGFILE11 (LPC43_BACKUP_BASE+LPC43_REGFILE11_OFFSET)
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#define LPC43_REGFILE12 (LPC43_BACKUP_BASE+LPC43_REGFILE12_OFFSET)
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#define LPC43_REGFILE13 (LPC43_BACKUP_BASE+LPC43_REGFILE13_OFFSET)
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#define LPC43_REGFILE14 (LPC43_BACKUP_BASE+LPC43_REGFILE14_OFFSET)
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#define LPC43_REGFILE15 (LPC43_BACKUP_BASE+LPC43_REGFILE15_OFFSET)
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#define LPC43_REGFILE16 (LPC43_BACKUP_BASE+LPC43_REGFILE16_OFFSET)
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#define LPC43_REGFILE17 (LPC43_BACKUP_BASE+LPC43_REGFILE17_OFFSET)
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#define LPC43_REGFILE18 (LPC43_BACKUP_BASE+LPC43_REGFILE18_OFFSET)
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#define LPC43_REGFILE19 (LPC43_BACKUP_BASE+LPC43_REGFILE19_OFFSET)
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#define LPC43_REGFILE20 (LPC43_BACKUP_BASE+LPC43_REGFILE20_OFFSET)
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#define LPC43_REGFILE21 (LPC43_BACKUP_BASE+LPC43_REGFILE21_OFFSET)
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#define LPC43_REGFILE22 (LPC43_BACKUP_BASE+LPC43_REGFILE22_OFFSET)
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#define LPC43_REGFILE23 (LPC43_BACKUP_BASE+LPC43_REGFILE23_OFFSET)
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#define LPC43_REGFILE24 (LPC43_BACKUP_BASE+LPC43_REGFILE24_OFFSET)
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#define LPC43_REGFILE25 (LPC43_BACKUP_BASE+LPC43_REGFILE25_OFFSET)
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#define LPC43_REGFILE26 (LPC43_BACKUP_BASE+LPC43_REGFILE26_OFFSET)
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#define LPC43_REGFILE27 (LPC43_BACKUP_BASE+LPC43_REGFILE27_OFFSET)
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#define LPC43_REGFILE28 (LPC43_BACKUP_BASE+LPC43_REGFILE28_OFFSET)
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#define LPC43_REGFILE29 (LPC43_BACKUP_BASE+LPC43_REGFILE29_OFFSET)
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#define LPC43_REGFILE30 (LPC43_BACKUP_BASE+LPC43_REGFILE30_OFFSET)
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#define LPC43_REGFILE31 (LPC43_BACKUP_BASE+LPC43_REGFILE31_OFFSET)
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#define LPC43_REGFILE32 (LPC43_BACKUP_BASE+LPC43_REGFILE32_OFFSET)
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#define LPC43_REGFILE33 (LPC43_BACKUP_BASE+LPC43_REGFILE33_OFFSET)
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#define LPC43_REGFILE34 (LPC43_BACKUP_BASE+LPC43_REGFILE34_OFFSET)
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#define LPC43_REGFILE35 (LPC43_BACKUP_BASE+LPC43_REGFILE35_OFFSET)
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#define LPC43_REGFILE36 (LPC43_BACKUP_BASE+LPC43_REGFILE36_OFFSET)
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#define LPC43_REGFILE37 (LPC43_BACKUP_BASE+LPC43_REGFILE37_OFFSET)
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#define LPC43_REGFILE38 (LPC43_BACKUP_BASE+LPC43_REGFILE38_OFFSET)
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#define LPC43_REGFILE39 (LPC43_BACKUP_BASE+LPC43_REGFILE39_OFFSET)
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#define LPC43_REGFILE40 (LPC43_BACKUP_BASE+LPC43_REGFILE40_OFFSET)
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#define LPC43_REGFILE41 (LPC43_BACKUP_BASE+LPC43_REGFILE41_OFFSET)
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#define LPC43_REGFILE42 (LPC43_BACKUP_BASE+LPC43_REGFILE42_OFFSET)
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#define LPC43_REGFILE43 (LPC43_BACKUP_BASE+LPC43_REGFILE43_OFFSET)
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#define LPC43_REGFILE44 (LPC43_BACKUP_BASE+LPC43_REGFILE44_OFFSET)
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#define LPC43_REGFILE45 (LPC43_BACKUP_BASE+LPC43_REGFILE45_OFFSET)
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#define LPC43_REGFILE46 (LPC43_BACKUP_BASE+LPC43_REGFILE46_OFFSET)
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#define LPC43_REGFILE47 (LPC43_BACKUP_BASE+LPC43_REGFILE47_OFFSET)
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#define LPC43_REGFILE48 (LPC43_BACKUP_BASE+LPC43_REGFILE48_OFFSET)
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#define LPC43_REGFILE49 (LPC43_BACKUP_BASE+LPC43_REGFILE49_OFFSET)
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#define LPC43_REGFILE50 (LPC43_BACKUP_BASE+LPC43_REGFILE50_OFFSET)
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#define LPC43_REGFILE51 (LPC43_BACKUP_BASE+LPC43_REGFILE51_OFFSET)
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#define LPC43_REGFILE52 (LPC43_BACKUP_BASE+LPC43_REGFILE52_OFFSET)
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#define LPC43_REGFILE53 (LPC43_BACKUP_BASE+LPC43_REGFILE53_OFFSET)
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#define LPC43_REGFILE54 (LPC43_BACKUP_BASE+LPC43_REGFILE54_OFFSET)
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#define LPC43_REGFILE55 (LPC43_BACKUP_BASE+LPC43_REGFILE55_OFFSET)
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#define LPC43_REGFILE56 (LPC43_BACKUP_BASE+LPC43_REGFILE56_OFFSET)
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#define LPC43_REGFILE57 (LPC43_BACKUP_BASE+LPC43_REGFILE57_OFFSET)
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#define LPC43_REGFILE58 (LPC43_BACKUP_BASE+LPC43_REGFILE58_OFFSET)
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#define LPC43_REGFILE59 (LPC43_BACKUP_BASE+LPC43_REGFILE59_OFFSET)
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#define LPC43_REGFILE60 (LPC43_BACKUP_BASE+LPC43_REGFILE60_OFFSET)
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#define LPC43_REGFILE61 (LPC43_BACKUP_BASE+LPC43_REGFILE61_OFFSET)
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#define LPC43_REGFILE62 (LPC43_BACKUP_BASE+LPC43_REGFILE62_OFFSET)
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#define LPC43_REGFILE63 (LPC43_BACKUP_BASE+LPC43_REGFILE63_OFFSET)
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/* Register bit definitions *********************************************************/
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/* Miscellaneous registers */
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/* Interrupt Location Register */
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#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */
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#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */
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/* Bits 2-31: Reserved */
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/* Clock Control Register */
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#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */
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#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */
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/* Bits 2-3: Internal test mode controls */
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#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */
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/* Bits 5-31: Reserved */
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/* Counter Increment Interrupt Register */
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#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */
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#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */
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#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */
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#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */
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#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */
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#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */
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#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */
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#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */
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/* Bits 8-31: Reserved */
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/* Alarm Mask Register */
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#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */
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#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */
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#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */
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#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */
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#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */
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#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */
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#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */
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#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */
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/* Bits 8-31: Reserved */
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/* Consolidated time registers */
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/* Consolidated Time Register 0 */
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#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */
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#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT)
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/* Bits 6-7: Reserved */
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#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */
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#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT)
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/* Bits 14-15: Reserved */
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#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */
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#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT)
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/* Bits 21-23: Reserved */
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#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */
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#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT)
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/* Bits 27-31: Reserved */
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/* Consolidated Time Register 1 */
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#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */
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#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT)
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/* Bits 5-7: Reserved */
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#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */
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#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT)
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/* Bits 12-15: Reserved */
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#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */
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#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT)
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/* Bits 28-31: Reserved */
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/* Consolidated Time Register 2 */
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#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */
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#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT)
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/* Bits 12-31: Reserved */
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/* Time counter registers */
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#define RTC_SEC_MASK (0x003f)
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#define RTC_MIN_MASK (0x003f)
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#define RTC_HOUR_MASK (0x001f)
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#define RTC_DOM_MASK (0x001f)
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#define RTC_DOW_MASK (0x0007)
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#define RTC_DOY_MASK (0x01ff)
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#define RTC_MONTH_MASK (0x000f)
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#define RTC_YEAR_MASK (0x0fff)
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/* Calibration Value Register */
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#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */
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#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT)
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#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */
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/* Bits 18-31: Reserved */
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/* Alarm register group */
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#define RTC_ASEC_MASK (0x003f)
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#define RTC_AMIN_MASK (0x003f)
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#define RTC_AHOUR_MASK (0x001f)
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#define RTC_ADOM_MASK (0x001f)
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#define RTC_ADOW_MASK (0x0007)
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#define RTC_ADOY_MASK (0x01ff)
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#define RTC_AMON_MASK (0x000f)
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#define RTC_AYEAR_MASK (0x0fff)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H */
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