281 lines
16 KiB
C
281 lines
16 KiB
C
/****************************************************************************
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* arch/mips/src/pic32mx/pic32mx_spi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_SPI_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_SPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "pic32mx_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define PIC32MX_SPI_CON_OFFSET 0x0000 /* SPI control register */
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#define PIC32MX_SPI_CONCLR_OFFSET 0x0004 /* SPI control clear register */
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#define PIC32MX_SPI_CONSET_OFFSET 0x0008 /* SPI control set register */
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#define PIC32MX_SPI_CONINV_OFFSET 0x000c /* SPI control invert register */
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#define PIC32MX_SPI_STAT_OFFSET 0x0010 /* SPI status register */
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#define PIC32MX_SPI_STATCLR_OFFSET 0x0014 /* SPI status clear register */
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#define PIC32MX_SPI_BUF_OFFSET 0x0020 /* SPI buffer register */
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#define PIC32MX_SPI_BRG_OFFSET 0x0030 /* SPI baud rate register */
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#define PIC32MX_SPI_BRGCLR_OFFSET 0x0034 /* SPI baud rate clear register */
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#define PIC32MX_SPI_BRGSET_OFFSET 0x0038 /* SPI baud rate set register */
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#define PIC32MX_SPI_BRGINV_OFFSET 0x003c /* SPI baud rate invert register */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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#define PIC32MX_SPI_CON2_OFFSET 0x0040 /* SPI control register 2*/
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#endif
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/* Register Addresses *******************************************************/
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#ifdef PIC32MX_SPI1_K1BASE
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# define PIC32MX_SPI1_CON (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CON_OFFSET)
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# define PIC32MX_SPI1_CONCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
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# define PIC32MX_SPI1_CONSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
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# define PIC32MX_SPI1_CONINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
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# define PIC32MX_SPI1_STAT (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STAT_OFFSET)
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# define PIC32MX_SPI1_STATCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STATCLR_OFFSET)
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# define PIC32MX_SPI1_BUF (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BUF_OFFSET)
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# define PIC32MX_SPI1_BRG (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRG_OFFSET)
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# define PIC32MX_SPI1_BRGCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
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# define PIC32MX_SPI1_BRGSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
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# define PIC32MX_SPI1_BRGINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
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# if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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# define PIC32MX_SPI1_CON2 (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CON2_OFFSET)
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# endif
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#endif
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#ifdef PIC32MX_SPI2_K1BASE
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# define PIC32MX_SPI2_CON (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CON_OFFSET)
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# define PIC32MX_SPI2_CONCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
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# define PIC32MX_SPI2_CONSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
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# define PIC32MX_SPI2_CONINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
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# define PIC32MX_SPI2_STAT (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STAT_OFFSET)
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# define PIC32MX_SPI2_STATCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STATCLR_OFFSET)
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# define PIC32MX_SPI2_BUF (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BUF_OFFSET)
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# define PIC32MX_SPI2_BRG (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRG_OFFSET)
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# define PIC32MX_SPI2_BRGCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
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# define PIC32MX_SPI2_BRGSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
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# define PIC32MX_SPI2_BRGINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
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# if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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# define PIC32MX_SPI2_CON2 (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CON2_OFFSET)
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# endif
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#endif
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#ifdef PIC32MX_SPI3_K1BASE
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# define PIC32MX_SPI3_CON (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CON_OFFSET)
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# define PIC32MX_SPI3_CONCLR (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
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# define PIC32MX_SPI3_CONSET (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
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# define PIC32MX_SPI3_CONINV (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
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# define PIC32MX_SPI3_STAT (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_STAT_OFFSET)
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# define PIC32MX_SPI3_STATCLR (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_STATCLR_OFFSET)
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# define PIC32MX_SPI3_BUF (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BUF_OFFSET)
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# define PIC32MX_SPI3_BRG (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRG_OFFSET)
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# define PIC32MX_SPI3_BRGCLR (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
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# define PIC32MX_SPI3_BRGSET (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
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# define PIC32MX_SPI3_BRGINV (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
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#endif
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#ifdef PIC32MX_SPI4_K1BASE
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# define PIC32MX_SPI4_CON (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CON_OFFSET)
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# define PIC32MX_SPI4_CONCLR (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
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# define PIC32MX_SPI4_CONSET (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
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# define PIC32MX_SPI4_CONINV (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
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# define PIC32MX_SPI4_STAT (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_STAT_OFFSET)
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# define PIC32MX_SPI4_STATCLR (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_STATCLR_OFFSET)
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# define PIC32MX_SPI4_BUF (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BUF_OFFSET)
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# define PIC32MX_SPI4_BRG (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRG_OFFSET)
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# define PIC32MX_SPI4_BRGCLR (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
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# define PIC32MX_SPI4_BRGSET (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
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# define PIC32MX_SPI4_BRGINV (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
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#endif
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/* Register Bit-Field Definitions *******************************************/
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/* SPI control register */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \
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defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
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# define SPI_CON_RTXISEL_SHIFT (0) /* Bits 0-1: SPI Receive Buffer Full Interrupt Mode */
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# define SPI_CON_RTXISEL_MASK (3 << SPI_CON_RTXISEL_SHIFT)
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# define SPI_CON_RTXISEL_EMPTY (0 << SPI_CON_RTXISEL_SHIFT) /* Buffer empty */
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# define SPI_CON_RTXISEL_NEMPTY (1 << SPI_CON_RTXISEL_SHIFT) /* Buffer not empty */
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# define SPI_CON_RTXISEL_HALF (2 << SPI_CON_RTXISEL_SHIFT) /* Buffer half full or more */
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# define SPI_CON_RTXISEL_FULL (3 << SPI_CON_RTXISEL_SHIFT) /* Buffer full */
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# define SPI_CON_STXISEL_SHIFT (2) /* Bits 2-3: SPI Transmit Buffer Empty Interrupt Mode */
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# define SPI_CON_STXISEL_MASK (3 << SPI_CON_STXISEL_SHIFT)
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# define SPI_CON_STXISEL_DONE (0 << SPI_CON_STXISEL_SHIFT) /* Buffer empty (and data shifted out) */
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# define SPI_CON_STXISEL_EMPTY (1 << SPI_CON_STXISEL_SHIFT) /* Buffer empty */
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# define SPI_CON_STXISEL_HALF (2 << SPI_CON_STXISEL_SHIFT) /* Buffer half empty or more */
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# define SPI_CON_STXISEL_NFULL (3 << SPI_CON_STXISEL_SHIFT) /* Buffer not full */
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#endif
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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# define SPI_CON_DISSDI (1 << 4) /* Bit 4: Disable SDI */
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#else
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/* Bit 4: Reserved */
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#endif
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#define SPI_CON_MSTEN (1 << 5) /* Bits 5: Master mode enable */
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#define SPI_CON_CKP (1 << 6) /* Bits 6: Clock polarity select */
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#define SPI_CON_SSEN (1 << 7) /* Bits 7: Slave select enable (slave mode) */
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#define SPI_CON_CKE (1 << 8) /* Bits 8: SPI clock edge select */
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#define SPI_CON_SMP (1 << 9) /* Bits 9: SPI data input sample phase */
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#define SPI_CON_MODE_SHIFT (10) /* Bits 10-11: 32/16-Bit Communication Select */
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#define SPI_CON_MODE_MASK (3 << SPI_CON_MODE_SHIFT)
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# define SPI_CON_MODE_8BIT (0 << SPI_CON_MODE_SHIFT) /* 8-bit data width */
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# define SPI_CON_MODE_16BIT (1 << SPI_CON_MODE_SHIFT) /* 16-bit data width */
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# define SPI_CON_MODE_32BIT (2 << SPI_CON_MODE_SHIFT) /* 32-bit data width */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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/* With AUDEN=1: */
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# define SPI_CON_MODE_161616 (0 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 16-bit channel */
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# define SPI_CON_MODE_161632 (1 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 32-bit channel */
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# define SPI_CON_MODE_323232 (2 << SPI_CON_MODE_SHIFT) /* 32-bit data, 32-bit FIFO, 32-bit channel */
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# define SPI_CON_MODE_243232 (3 << SPI_CON_MODE_SHIFT) /* 24-bit data, 32-bit FIFO, 32-bit channel */
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#endif
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#define SPI_CON_DISSDO (1 << 12) /* Bits 12: Disable SDOx pin */
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#define SPI_CON_SIDL (1 << 13) /* Bits 13: Stop in idle mode */
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#if !defined(CHIP_PIC32MX1) && !defined(CHIP_PIC32MX2)
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# define SPI_CON_FRZ (1 << 14) /* Bits 14: Freeze in debug exception */
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#endif
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#define SPI_CON_ON (1 << 15) /* Bits 15: SPI peripheral on */
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#define SPI_CON_ENHBUF (1 << 16) /* Bits 16: Enhanced buffer enable */
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#define SPI_CON_SPIFE (1 << 17) /* Bits 17: Frame sync pulse edge select */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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/* Bits 18-22: Reserved */
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# define SPI_CON_MCLKSEL (1 << 18) /* Master clock enable */
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#else
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/* Bits 18-23: Reserved */
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#endif
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \
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defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
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# define SPI_CON_FRMCNT_SHIFT (24) /* Bits 24-26: Frame Sync Pulse Counter bits */
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# define SPI_CON_FRMCNT_MASK (7 << SPI_CON_FRMCNT_SHIFT)
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# define SPI_CON_FRMCNT_CHAR1 (0 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse each char */
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# define SPI_CON_FRMCNT_CHAR2 (1 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 2 chars */
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# define SPI_CON_FRMCNT_CHAR4 (2 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 4 chars */
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# define SPI_CON_FRMCNT_CHAR8 (3 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 8 chars */
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# define SPI_CON_FRMCNT_CHAR16 (4 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 16 chars */
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# define SPI_CON_FRMCNT_CHAR32 (5 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 32 chars */
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# define SPI_CON_FRMSYPW (1 << 27) /* Bits 27: Frame sync pulse width */
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# define SPI_CON_MSSEN (1 << 28) /* Bits 28: Master mode slave select enable */
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#endif
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#define SPI_CON_FRMPOL (1 << 29) /* Bits 29: Frame sync polarity */
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#define SPI_CON_FRMSYNC (1 << 30) /* Bits 30: Frame sync pulse direction control on SSx pin */
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#define SPI_CON_FRMEN (1 << 31) /* Bits 31: Framed SPI support */
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/* SPI control register 2 */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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# define SPI2_CON2_AUDMOD_SHIFT (0) /* Bits 0-1: Audio Protocol Mode */
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# define SPI2_CON2_AUDMOD_MASK (3 << SPI2_CON2_AUDMOD_SHIFT)
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# define SPI2_CON2_AUDMOD_I2S (0 << SPI2_CON2_AUDMOD_SHIFT) /* I2S mode */
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# define SPI2_CON2_AUDMOD_LJ (1 << SPI2_CON2_AUDMOD_SHIFT) /* Left Justified mode */
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# define SPI2_CON2_AUDMOD_RJ (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */
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# define SPI2_CON2_AUDMOD_PCM (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */
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/* Bit 2: Reserved */
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# define SPI2_CON2_AUDMONO (1 << 3) /* Bit 3: Transmit Audio Data Format */
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/* Bits 5-6: Reserved */
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# define SPI2_CON2_AUDEN (1 << 7) /* Bit 7: Enable Audio CODEC Support */
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# define SPI2_CON2_IGNTUR (1 << 8) /* Bit 8: Ignore Transmit Underrun bit */
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# define SPI2_CON2_IGNROV (1 << 9) /* Bit 9: Ignore Receive Overflow */
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# define SPI2_CON2_SPITUREN (1 << 10) /* Bit 10: Enable Interrupt Events via SPITUR */
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# define SPI2_CON2_SPIROVEN (1 << 11) /* Bit 11: Enable Interrupt Events via SPIROV */
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# define SPI2_CON2_FRMERREN (1 << 12) /* Bit 12: Enable Interrupt Events via FRMERR */
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/* Bits 13-14: Reserved */
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# define SPI2_CON2_SPISGNEXT (1 << 15) /* Bit 15 : Sign Extend Read Data from the RX FIFO */
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/* Bits 16-31: Reserved */
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#endif
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/* SPI status register */
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#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
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# define SPI_STAT_SPIRBF (1 << 0) /* Bit 0: SPI receive buffer full status */
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# define SPI_STAT_SPITBE (1 << 3) /* Bit 3: SPI transmit buffer empty status */
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# define SPI_STAT_SPIROV (1 << 6) /* Bit 6: Receive overflow flag */
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# define SPI_STAT_SPIBUSY (1 << 11) /* Bit 11: SPI activity status */
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#elif defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \
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defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
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# define SPI_STAT_SPIRBF (1 << 0) /* Bit 0: SPI receive buffer full status */
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# define SPI_STAT_SPITBF (1 << 1) /* Bit 1: SPI transmit buffer full status */
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# define SPI_STAT_SPITBE (1 << 3) /* Bit 3: SPI transmit buffer empty status */
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# define SPI_STAT_SPIRBE (1 << 5) /* Bit 5: RX FIFO Empty */
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# define SPI_STAT_SPIROV (1 << 6) /* Bit 6: Receive overflow flag */
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# define SPI_STAT_SRMT (1 << 7) /* Bit 6: Shift Register Empty */
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# define SPI_STAT_SPITUR (1 << 8) /* Bit 8: Transmit under run */
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# define SPI_STAT_SPIBUSY (1 << 11) /* Bit 11: SPI activity status */
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# if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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# define SPI_STAT_FRMERR (1 << 12) /* Bit 12: SPI Frame Error status */
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# endif
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# define SPI_STAT_TXBUFELM_SHIFT (16) /* Bits 16-20: Transmit Buffer Element Count bits */
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# define SPI_STAT_TXBUFELM_MASK (31 << SPI_STAT_TXBUFELM_SHIFT)
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# define SPI_STAT_RXBUFELM_SHIFT (24) /* Bits 24-28: Receive Buffer Element Count bits */
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# define SPI_STAT_RXBUFELM_MASK (31 << SPI_STAT_RXBUFELM_SHIFT)
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#endif
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/* SPI buffer register (32-bits wide) */
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/* SPI baud rate register */
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#define SPI_BRG_MASK 0x1ff
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_SPI_H */
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