zhuyanlin 5af1b671b6 armv7-a/armv7-r:cache: modify hardcode in cache set/way operation ... Some chip not use the default cache size & way , read from CCSIDR instead of hardcode. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>		2022-03-03 14:11:31 +08:00
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include	arch: Remove SYS_RESERVED from Kconfg	2022-02-27 22:54:13 +08:00
src	armv7-a/armv7-r:cache: modify hardcode in cache set/way operation	2022-03-03 14:11:31 +08:00
Kconfig	arch, board: Add thumb support to i.MX6	2022-02-25 10:51:12 +08:00