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nuttx/arch/arm/src/samv7
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Stefan Kolb d44ecbcfbb This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. 
In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it.
2016-05-27 07:51:50 -06:00
..
chip Fix a copy and paste error concerning the CAN driver. In the file sam_matrix.h the define SAM_MATRIX_CAN0_OFFSET is set to the wrong value. 2016-05-06 04:02:28 -06:00
chip.h SAMV7 EMAC: Fix alignment issue: RX buffers need to be invalidated. This means the alignment of buffers must be at least to the data cache line size at both ends of the buffer 2015-03-28 13:09:01 -06:00
Kconfig This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. 2016-05-27 07:51:50 -06:00
Make.defs Add the up_systemreset interface to the samv7 arch. The approach is slightly different in that: 1) It enables ARCH_HAVE_RESET and allows the user to set if, and for how long, to drive External nRST signal. It also does not contain a default board_reset, as that really should be done in the config's src if CONFIG_BOARDCTL_RESET is defined. 2016-05-23 17:05:02 -06:00
sam_allocateheap.c Rename board_led_on to board_autoled_on 2015-11-01 09:07:06 -06:00
sam_clockconfig.c SAMV71 and SAME70: Place the Main Oscillator Enable in the board.h 2016-03-04 12:31:54 -06:00
sam_clockconfig.h SAMV7 USB: USB must be enabled before PMC 480MHz clock is enabled 2015-08-11 15:48:26 -06:00
sam_config.h Remove CONFIG_USARTn_ISUART 2016-05-25 11:21:48 -06:00
sam_emac.c Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
sam_ethernet.c SAMV7: Quick'n'dirty port of the SAMA5D4 Ethernet MAC driver to the SAMV7. Still some unresovled issues with DCache handling 2015-03-16 13:51:37 -06:00
sam_ethernet.h SAMV7: Add a sneak internal interface that will allow us to set the MAC address before NSH even starts 2015-03-18 17:23:40 -06:00
sam_freerun.c Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
sam_freerun.h SAM3/4, SAMA5, SAMv7 Tickless: Refuse to call lower-level timer logic if not yet initialized 2016-02-05 10:22:11 -06:00
sam_gpio.c Fix build if the config is not updated 2016-05-19 12:44:58 -10:00
sam_gpio.h Adds a JTAG config and ERASE config to Kconfig to set the CCFG_SYSIO SYSIO Pins 2016-05-19 14:33:54 -06:00
sam_gpioirq.c Correct some spacing issues 2015-10-07 11:39:06 -06:00
sam_hsmci_clkdiv.c Remove executable flag from more .c and .h files 2015-04-09 08:20:57 -06:00
sam_hsmci.c Cosmetic: Remove some harmless kruft left in last commit 2016-02-22 16:58:42 -06:00
sam_hsmci.h Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
sam_irq.c ARM: Fix missing header file. Update comments in all *_irq.c files. 2016-03-09 15:08:58 -06:00
sam_lowputc.c Backing out part of last commit 2016-05-19 15:46:07 -06:00
sam_lowputc.h Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
sam_mcan.c SAMV7: MCAN: Correct typo in MCAN0 configuration 2016-03-11 12:30:57 -06:00
sam_mcan.h Standardize the width of all comment boxes in header files 2015-10-02 17:47:23 -06:00
sam_mpuinit.c Rename CONFIG_ARMV7M_MPU to CONFIG_ARM_MPU so that we can reuse the configuration settings for the ARMV7R MPU 2015-12-14 13:56:21 -06:00
sam_mpuinit.h Rename CONFIG_ARMV7M_MPU to CONFIG_ARM_MPU so that we can reuse the configuration settings for the ARMV7R MPU 2015-12-14 13:56:21 -06:00
sam_oneshot.c This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. 2016-05-27 07:51:50 -06:00
sam_oneshot.h This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. 2016-05-27 07:51:50 -06:00
sam_pck.c SAMV7: Add support for PCK6 as a timer/counter clock source 2015-12-04 10:49:20 -06:00
sam_pck.h SAMV7: Extend programmable clock support for queries about the PCK configuration 2015-12-03 14:11:39 -06:00
sam_periphclks.h arch/arm/src/samv7: Add SAME70 memory map 2015-11-14 12:01:28 -06:00
sam_progmem.c arch/arm/src/samv7: Add SAME70 memory map 2015-11-14 12:01:28 -06:00
sam_progmem.h SAMV7 flash logic is complete, uncompiled, and untested 2015-11-12 10:46:59 -06:00
sam_qspi.c Trivial simplification to logic of last commit 2015-11-11 15:17:36 -06:00
sam_qspi.h SAMV71 QSPI: Use new QSPI interface. Can't use SPI interface as planned; the hardware architectue is too different 2015-08-25 15:23:59 -06:00
sam_rswdt.c SAM WDT: Rename up_wdginitialize() functions to something more appropriate for the internal OS interface. 2016-05-18 19:47:48 -06:00
sam_serial.c Remove CONFIG_USARTn_ISUART 2016-05-25 11:21:48 -06:00
sam_spi_slave.c Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
sam_spi.c SAMV7 SPI: Revise support for Peripheral Chip Select Decoding to address up to 15 slaved 2016-02-25 08:13:33 -06:00
sam_spi.h SAMV7 SPI: Revise support for Peripheral Chip Select Decoding to address up to 15 slaved 2016-02-25 08:13:33 -06:00
sam_ssc.c Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
sam_ssc.h SAMV71: Quick'n'dirty port of the SAMA5 SSC driver to the SAM7. The IP is compatible but there are still some DMA- and Cache-related issues that need to be worked out. 2015-03-12 16:00:38 -06:00
sam_start.c Fix build if the config is not updated 2016-05-19 12:44:58 -10:00
sam_start.h Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
sam_systemreset.c Restore PR. I have no idea where it went. 2016-05-23 17:45:15 -06:00
sam_tc.c Fix what I believe to be typos in SAMV7 timer 2016-03-08 17:26:01 -06:00
sam_tc.h SAMV7: Add support for PCK6 as a timer/counter clock source 2015-12-04 10:49:20 -06:00
sam_tickless.c This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. 2016-05-27 07:51:50 -06:00
sam_timerisr.c Costmetic fixes to C coding style 2015-10-05 17:13:53 -06:00
sam_trng.c SAMV7: Port SAMAD5 TRNG driver to the SAMV7 2015-12-06 08:53:31 -06:00
sam_trng.h SAMV7: Port SAMAD5 TRNG driver to the SAMV7 2015-12-06 08:53:31 -06:00
sam_twihs.c This patch ensures that the TWIHS (i2c) hw get's its clock set when the sequence of 2016-05-23 13:38:34 -06:00
sam_twihs.h Rename up_i2c initialize and uninitialize functions using the correct MCU-specific naming 2016-02-02 12:08:23 -06:00
sam_usbdev.h SAMV7: A little more USB-related stuff 2015-03-21 08:54:01 -06:00
sam_usbdevhs.c SAMV7: USBHS: Remove disabling of whole usb on suspend 2016-05-25 07:20:48 -06:00
sam_userspace.c SAMV7 protected mode: Don't enable D-Cache until userspace data has been initialized 2015-11-07 09:35:23 -06:00
sam_userspace.h Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
sam_wdt.c SAM WDT: Rename up_wdginitialize() functions to something more appropriate for the internal OS interface. 2016-05-18 19:47:48 -06:00
sam_wdt.h SAM WDT: Rename up_wdginitialize() functions to something more appropriate for the internal OS interface. 2016-05-18 19:47:48 -06:00
sam_xdmac.c SAM (all): Fix several places in DMA logic where a spurious semicolon causes bad conditional logic 2016-05-11 17:26:59 -06:00
sam_xdmac.h SAMV7 XDMAC: Don't sample interrupt status registers in debug mode. This can cause loss of interrupts 2015-11-07 11:25:20 -06:00
same70_periphclks.h arch/arm/src/samv7: Add SAME70 memory map 2015-11-14 12:01:28 -06:00
samv71_periphclks.h arch/arm/src/samv7: Add support for SAME70 peripheral clocks 2015-11-14 11:41:53 -06:00