177 lines
5.3 KiB
C
177 lines
5.3 KiB
C
/****************************************************************************
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* arch/arm/src/armv8-m/fpb.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV8_M_FPB_H
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#define __ARCH_ARM_SRC_ARMV8_M_FPB_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Flash Patch and Breakpoint Unit FPB **************************************/
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/* FPB Register Base Address ************************************************/
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#define FPB_BASE 0xe0002000
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/* FPB Register Offsets *****************************************************/
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#define FPB_CTRL_OFFSET 0x0000 /* Control */
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#define FPB_REMAP_OFFSET 0x0004 /* Remap */
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#define FPB_COMP0_OFFSET 0x0008 /* Comparator 0 */
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#define FPB_COMP1_OFFSET 0x000c /* Comparator 1 */
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#define FPB_COMP2_OFFSET 0x0010 /* Comparator 2 */
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#define FPB_COMP3_OFFSET 0x0014 /* Comparator 3 */
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#define FPB_COMP4_OFFSET 0x0018 /* Comparator 4 */
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#define FPB_COMP5_OFFSET 0x001C /* Comparator 5 */
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#define FPB_COMP6_OFFSET 0x0020 /* Comparator 6 */
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#define FPB_COMP7_OFFSET 0x0024 /* Comparator 7 */
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/* FPB Register Addresses ***************************************************/
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#define FPB_CTRL (FPB_BASE + FPB_CTRL_OFFSET)
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#define FPB_REMAP (FPB_BASE + FPB_REMAP_OFFSET)
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#define FPB_COMP0 (FPB_BASE + FPB_COMP0_OFFSET)
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#define FPB_COMP1 (FPB_BASE + FPB_COMP1_OFFSET)
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#define FPB_COMP2 (FPB_BASE + FPB_COMP2_OFFSET)
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#define FPB_COMP3 (FPB_BASE + FPB_COMP3_OFFSET)
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#define FPB_COMP4 (FPB_BASE + FPB_COMP4_OFFSET)
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#define FPB_COMP5 (FPB_BASE + FPB_COMP5_OFFSET)
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#define FPB_COMP6 (FPB_BASE + FPB_COMP6_OFFSET)
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#define FPB_COMP7 (FPB_BASE + FPB_COMP7_OFFSET
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/* FPB Register Bitfield Definitions ****************************************/
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/* FPB_CTRL */
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/* NUM_CODE2
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*
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* Number of full banks of code comparators, sixteen comparators per bank.
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* Where less than sixteen code comparators are provided, the bank count is
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* zero, and the number present indicated by NUM_CODE1. This read only field
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* contains 3'b000 to indicate 0 banks for Cortex-M processor.
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*/
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#define FPB_CTRL_NUM_CODE2_SHIFT 12
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#define FPB_CTRL_NUM_CODE2_MASK 0x00007000
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/* NUM_LIT
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*
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* Number of literal slots field.
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*
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* 0: No literal slots
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* 2: Two literal slots
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*/
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#define FPB_CTRL_NUM_LIT_SHIFT 8
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#define FPB_CTRL_NUM_LIT_MASK 0x00000f00
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/* NUM_CODE1
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*
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* Number of code slots field.
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*
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* 0: No code slots
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* 2: Two code slots
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* 6: Six code slots
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*/
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#define FPB_CTRL_NUM_CODE1_SHIFT 4
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#define FPB_CTRL_NUM_CODE1_MASK 0x000000f0
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/* KEY
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*
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* Key field. In order to write to this register, this bit-field must be
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* written to '1'. This bit always reads 0.
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*/
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#define FPB_CTRL_KEY_SHIFT 1
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#define FPB_CTRL_KEY_MASK 0x00000002
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# define FPB_CTRL_KEY 0x00000002
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/* ENABLE
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*
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* Flash patch unit enable bit
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*
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* 0: Flash patch unit disabled
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* 1: Flash patch unit enabled
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*/
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#define FPB_CTRL_ENABLE_SHIFT 0
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#define FPB_CTRL_ENABLE_MASK 0x00000001
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# define FPB_CTRL_ENABLE 0x00000001
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/* FPB_REMAP */
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/* REMAP
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*
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* Remap base address field.
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*/
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#define FPB_REMAP_REMAP_SHIFT 5
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#define FPB_REMAP_REMAP_MASK 0x1fffffe0
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/* REMAP
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*
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* Remap supported field.
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*/
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#define FPB_REMAP_RMPSPT_SHIFT 29
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#define FPB_REMAP_RMPSPT_MASK 0x20000000
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# define FPB_REMAP_RMPSPT 0x20000000
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/* FPB_COMP0 - FPB_COMP7 */
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/* REPLACE
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*
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* This selects what happens when the COMP address is matched. Address
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* remapping only takes place for the 0x0 setting.
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*
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* 0: Remap to remap address. See REMAP.REMAP
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* 1: Set BKPT on lower halfword, upper is unaffected
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* 2: Set BKPT on upper halfword, lower is unaffected
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* 3: Set BKPT on both lower and upper halfwords.
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*/
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#define FPB_COMP0_REPLACE_SHIFT 30
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#define FPB_COMP0_REPLACE_MASK 0xc0000000
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/* COMP
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*
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* Comparison address.
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*/
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#define FPB_COMP0_COMP_SHIFT 2
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#define FPB_COMP0_COMP_MASK 0x1ffffffc
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/* ENABLE
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*
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* Compare and remap enable comparator. CTRL.ENABLE must also be set to
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* enable comparisons.
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*
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* 0: Compare and remap for comparator 0 disabled
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* 1: Compare and remap for comparator 0 enabled
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*/
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#define FPB_COMP0_ENABLE_MASK 0x00000001
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#define FPB_COMP0_ENABLE_SHIFT 0
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# define FPB_COMP0_ENABLE 0x00000001
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#endif /* __ARCH_ARM_SRC_ARMV8_M_FPB_H */
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