202 lines
9.5 KiB
C
202 lines
9.5 KiB
C
/****************************************************************************
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* arch/arm/src/armv8-m/tpi.h
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*
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* Copyright (c) 2009 - 2013 ARM LIMITED
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*
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS
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* AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
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* Author: Pierre-noel Bouteville <pnb990@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV8_M_TPI_H
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#define __ARCH_ARM_SRC_ARMV8_M_TPI_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Trace Port Interface Register (TPI) Definitions **************************/
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/* TPI Register Base Address ************************************************/
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#define TPI_BASE (0xe0040000ul)
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/* TPI Register Addresses ***************************************************/
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#define TPI_SSPSR (TPI_BASE + 0x0000) /* Supported Parallel Port Size Register */
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#define TPI_CSPSR (TPI_BASE + 0x0004) /* Current Parallel Port Size Register */
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#define TPI_ACPR (TPI_BASE + 0x0010) /* Asynchronous Clock Prescaler Register */
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#define TPI_SPPR (TPI_BASE + 0x00f0) /* Selected Pin Protocol Register */
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#define TPI_FFSR (TPI_BASE + 0x0300) /* Formatter and Flush Status Register */
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#define TPI_FFCR (TPI_BASE + 0x0304) /* Formatter and Flush Control Register */
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#define TPI_FSCR (TPI_BASE + 0x0308) /* Formatter Synchronization Counter Register */
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#define TPI_TRIGGER (TPI_BASE + 0x0ee8) /* TRIGGER */
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#define TPI_FIFO0 (TPI_BASE + 0x0eec) /* Integration ETM Data */
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#define TPI_ITATBCTR2 (TPI_BASE + 0x0ef0) /* ITATBCTR2 */
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#define TPI_ITATBCTR0 (TPI_BASE + 0x0ef8) /* ITATBCTR0 */
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#define TPI_FIFO1 (TPI_BASE + 0x0efc) /* Integration ITM Data */
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#define TPI_ITCTRL (TPI_BASE + 0x0f00) /* Integration Mode Control */
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#define TPI_CLAIMSET (TPI_BASE + 0x0fa0) /* Claim tag set */
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#define TPI_CLAIMCLR (TPI_BASE + 0x0fa4) /* Claim tag clear */
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#define TPI_DEVID (TPI_BASE + 0x0fc8) /* TPIU_DEVID */
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#define TPI_DEVTYPE (TPI_BASE + 0x0fcc) /* TPIU_DEVTYPE */
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/* TPI Register Bit Field Definitions ***************************************/
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/* TPI ACPR */
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#define TPI_ACPR_PRESCALER_SHIFT 0
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#define TPI_ACPR_PRESCALER_MASK (0x1ffful << TPI_ACPR_PRESCALER_SHIFT)
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/* TPI SPPR */
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#define TPI_SPPR_TXMODE_SHIFT 0
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#define TPI_SPPR_TXMODE_MASK (0x3ul << TPI_SPPR_TXMODE_SHIFT)
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/* TPI FFSR */
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#define TPI_FFSR_FtNonStop_SHIFT 3
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#define TPI_FFSR_FtNonStop_MASK (0x1ul << TPI_FFSR_FtNonStop_SHIFT)
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#define TPI_FFSR_TCPresent_SHIFT 2
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#define TPI_FFSR_TCPresent_MASK (0x1ul << TPI_FFSR_TCPresent_SHIFT)
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#define TPI_FFSR_FtStopped_SHIFT 1
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#define TPI_FFSR_FtStopped_MASK (0x1ul << TPI_FFSR_FtStopped_SHIFT)
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#define TPI_FFSR_FlInProg_SHIFT 0
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#define TPI_FFSR_FlInProg_MASK (0x1ul << TPI_FFSR_FlInProg_SHIFT)
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/* TPI FFCR */
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#define TPI_FFCR_TrigIn_SHIFT 8
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#define TPI_FFCR_TrigIn_MASK (0x1ul << TPI_FFCR_TrigIn_SHIFT)
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#define TPI_FFCR_EnFCont_SHIFT 1
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#define TPI_FFCR_EnFCont_MASK (0x1ul << TPI_FFCR_EnFCont_SHIFT)
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#define TPI_TRIGGER_TRIGGER_SHIFT 0
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#define TPI_TRIGGER_TRIGGER_MASK (0x1ul << TPI_TRIGGER_TRIGGER_SHIFT)
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/* TPI FIFO0 */
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#define TPI_FIFO0_ITM_ATVALID_SHIFT 29
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#define TPI_FIFO0_ITM_ATVALID_MASK (0x3ul << TPI_FIFO0_ITM_ATVALID_SHIFT)
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#define TPI_FIFO0_ITM_bytecount_SHIFT 27
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#define TPI_FIFO0_ITM_bytecount_MASK (0x3ul << TPI_FIFO0_ITM_bytecount_SHIFT)
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#define TPI_FIFO0_ETM_ATVALID_SHIFT 26
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#define TPI_FIFO0_ETM_ATVALID_MASK (0x3ul << TPI_FIFO0_ETM_ATVALID_SHIFT)
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#define TPI_FIFO0_ETM_bytecount_SHIFT 24
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#define TPI_FIFO0_ETM_bytecount_MASK (0x3ul << TPI_FIFO0_ETM_bytecount_SHIFT)
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#define TPI_FIFO0_ETM2_SHIFT 16
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#define TPI_FIFO0_ETM2_MASK (0xfful << TPI_FIFO0_ETM2_SHIFT)
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#define TPI_FIFO0_ETM1_SHIFT 8
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#define TPI_FIFO0_ETM1_MASK (0xfful << TPI_FIFO0_ETM1_SHIFT)
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#define TPI_FIFO0_ETM0_SHIFT 0
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#define TPI_FIFO0_ETM0_MASK (0xfful << TPI_FIFO0_ETM0_SHIFT)
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/* TPI ITATBCTR2 */
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#define TPI_ITATBCTR2_ATREADY_SHIFT 0
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#define TPI_ITATBCTR2_ATREADY_MASK (0x1ul << TPI_ITATBCTR2_ATREADY_SHIFT)
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/* TPI FIFO1 */
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#define TPI_FIFO1_ITM_ATVALID_SHIFT 29
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#define TPI_FIFO1_ITM_ATVALID_MASK (0x3ul << TPI_FIFO1_ITM_ATVALID_SHIFT)
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#define TPI_FIFO1_ITM_bytecount_SHIFT 27
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#define TPI_FIFO1_ITM_bytecount_MASK (0x3ul << TPI_FIFO1_ITM_bytecount_SHIFT)
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#define TPI_FIFO1_ETM_ATVALID_SHIFT 26
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#define TPI_FIFO1_ETM_ATVALID_MASK (0x3ul << TPI_FIFO1_ETM_ATVALID_SHIFT)
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#define TPI_FIFO1_ETM_bytecount_SHIFT 24
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#define TPI_FIFO1_ETM_bytecount_MASK (0x3ul << TPI_FIFO1_ETM_bytecount_SHIFT)
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#define TPI_FIFO1_ITM2_SHIFT 16
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#define TPI_FIFO1_ITM2_MASK (0xfful << TPI_FIFO1_ITM2_SHIFT)
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#define TPI_FIFO1_ITM1_SHIFT 8
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#define TPI_FIFO1_ITM1_MASK (0xfful << TPI_FIFO1_ITM1_SHIFT)
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#define TPI_FIFO1_ITM0_SHIFT 0
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#define TPI_FIFO1_ITM0_MASK (0xfful << TPI_FIFO1_ITM0_SHIFT)
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/* TPI ITATBCTR0 */
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#define TPI_ITATBCTR0_ATREADY_SHIFT 0
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#define TPI_ITATBCTR0_ATREADY_MASK (0x1ul << TPI_ITATBCTR0_ATREADY_SHIFT)
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/* TPI ITCTRL */
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#define TPI_ITCTRL_Mode_SHIFT 0
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#define TPI_ITCTRL_Mode_MASK (0x1ul << TPI_ITCTRL_Mode_SHIFT)
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/* TPI DEVID */
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#define TPI_DEVID_NRZVALID_SHIFT 11
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#define TPI_DEVID_NRZVALID_MASK (0x1ul << TPI_DEVID_NRZVALID_SHIFT)
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#define TPI_DEVID_MANCVALID_SHIFT 10
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#define TPI_DEVID_MANCVALID_MASK (0x1ul << TPI_DEVID_MANCVALID_SHIFT)
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#define TPI_DEVID_PTINVALID_SHIFT 9
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#define TPI_DEVID_PTINVALID_MASK (0x1ul << TPI_DEVID_PTINVALID_SHIFT)
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#define TPI_DEVID_MinBufSz_SHIFT 6
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#define TPI_DEVID_MinBufSz_MASK (0x7ul << TPI_DEVID_MinBufSz_SHIFT)
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#define TPI_DEVID_AsynClkIn_SHIFT 5
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#define TPI_DEVID_AsynClkIn_MASK (0x1ul << TPI_DEVID_AsynClkIn_SHIFT)
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#define TPI_DEVID_NrTraceInput_SHIFT 0
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#define TPI_DEVID_NrTraceInput_MASK (0x1ful << TPI_DEVID_NrTraceInput_SHIFT)
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/* TPI DEVTYPE */
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#define TPI_DEVTYPE_SubType_SHIFT 0
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#define TPI_DEVTYPE_SubType_MASK (0xful << TPI_DEVTYPE_SubType_SHIFT)
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#define TPI_DEVTYPE_MajorType_SHIFT 4
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#define TPI_DEVTYPE_MajorType_MASK (0xful << TPI_DEVTYPE_MajorType_SHIFT)
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#endif /* __ARCH_ARM_SRC_ARMV8_M_TPI_H */
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