73 lines
3.3 KiB
C
73 lines
3.3 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-m/psr.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_M_PSR_H
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#define __ARCH_ARM_SRC_ARMV7_M_PSR_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Application Program Status Register (APSR) */
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#define ARMV7M_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
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#define ARMV7M_APSR_V (1 << 28) /* Bit 28: Overflow flag */
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#define ARMV7M_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
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#define ARMV7M_APSR_Z (1 << 30) /* Bit 30: Zero flag */
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#define ARMV7M_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */
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/* Interrupt Program Status Register (IPSR) */
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#define ARMV7M_IPSR_ISR_SHIFT 0 /* Bits 8-0: ISR number */
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#define ARMV7M_IPSR_ISR_MASK (0x1ff << ARMV7M_IPSR_ISR_SHIFT)
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/* Execution PSR Register (EPSR) */
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#define ARMV7M_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
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#define ARMV7M_EPSR_ICIIT1_MASK (3 << ARMV7M_EPSR_ICIIT1_SHIFT)
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#define ARMV7M_EPSR_T (1 << 24) /* Bit 24: T-bit */
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#define ARMV7M_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
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#define ARMV7M_EPSR_ICIIT2_MASK (3 << ARMV7M_EPSR_ICIIT2_SHIFT)
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/* Save xPSR bits */
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#define ARMV7M_XPSR_ISR_SHIFT ARMV7M_IPSR_ISR_SHIFT
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#define ARMV7M_XPSR_ISR_MASK ARMV7M_IPSR_ISR_MASK
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#define ARMV7M_XPSR_ICIIT1_SHIFT ARMV7M_EPSR_ICIIT1_SHIFT/
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#define ARMV7M_XPSR_ICIIT1_MASK ARMV7M_EPSR_ICIIT1_MASK
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#define ARMV7M_XPSR_T ARMV7M_EPSR_T
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#define ARMV7M_XPSR_ICIIT2_SHIFT ARMV7M_EPSR_ICIIT2_SHIFT
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#define ARMV7M_XPSR_ICIIT2_MASK ARMV7M_EPSR_ICIIT2_MASK
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#define ARMV7M_XPSR_Q ARMV7M_APSR_Q
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#define ARMV7M_XPSR_V ARMV7M_APSR_V
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#define ARMV7M_XPSR_C ARMV7M_APSR_C
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#define ARMV7M_XPSR_Z ARMV7M_APSR_Z
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#define ARMV7M_XPSR_N ARMV7M_APSR_N
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_ARMV7_M_PSR_H */
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