a762c06ed9
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle against .c and .h files and fix it
Author: Juha Niskanen <juha.niskanen@haltian.com>
Fix typos and some incorrect comments
132 lines
5.2 KiB
C
132 lines
5.2 KiB
C
/****************************************************************************
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* arch/risc-v/include/spinlock.h
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*
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* Copyright (C) 2020 Masayuki Ishikawa. All rights reserved.
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* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
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*
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* Based on arch/arm/include/armv7-m/spinlock.h
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_SPINLOCK_H
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#define __ARCH_RISCV_INCLUDE_SPINLOCK_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif /* __ASSEMBLY__ */
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/* Include RISC-V architecture-specific IRQ definitions (including register
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* save structure and up_irq_save()/up_irq_restore() functions)
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*/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Spinlock states */
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#define SP_UNLOCKED 0 /* The Un-locked state */
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#define SP_LOCKED 1 /* The Locked state */
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/* Memory barriers for use with NuttX spinlock logic
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*
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* Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
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* explicit memory accesses that appear in program order before the DMB
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* instruction are observed before any explicit memory accesses that appear
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* in program order after the DMB instruction. It does not affect the
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* ordering of any other instructions executing on the processor
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*
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* Data Synchronization Barrier (DSB) acts as a special kind of memory
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* barrier. No instruction in program order after this instruction executes
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* until this instruction completes. This instruction completes when: (1) All
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* explicit memory accesses before this instruction complete, and (2) all
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* Cache, Branch predictor and TLB maintenance operations before this
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* instruction complete.
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*
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*/
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#define SP_DSB(n) __asm__ __volatile__ ("fence")
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#define SP_DMB(n) __asm__ __volatile__ ("fence")
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* The Type of a spinlock.
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*
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* RISC-V architecture (in the standard atomic-instruction extension "A")
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* supports exclusive accesses to memory locations in the form of the
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* Load-Reserved (LR) and Store-Conditional (SC) instructions. RV64 supports
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* doubleword aligned data only but others supports word aligned data.
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*
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* RISC-V architecture supports fence instruction to ensure memory ordering
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*/
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#ifdef __LP64__
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typedef uint64_t spinlock_t;
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#else
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typedef uint32_t spinlock_t;
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_testset
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*
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* Description:
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* Perform an atomic test and set operation on the provided spinlock.
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*
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* This function must be provided via the architecture-specific logic.
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*
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* Input Parameters:
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* lock - The address of spinlock object.
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*
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* Returned Value:
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* The spinlock is always locked upon return. The value of previous value
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* of the spinlock variable is returned, either SP_LOCKED if the spinlock
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* as previously locked (meaning that the test-and-set operation failed to
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* obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
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* (meaning that we successfully obtained the lock)
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*
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****************************************************************************/
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/* See prototype in nuttx/include/nuttx/spinlock.h */
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_RISCV_INCLUDE_SPINLOCK_H */
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