131 lines
4.9 KiB
C
131 lines
4.9 KiB
C
/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_psram.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H
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#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H
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#define PSRAM_SIZE_2MB (2 * 1024 * 1024)
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#define PSRAM_SIZE_4MB (4 * 1024 * 1024)
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#define PSRAM_SIZE_8MB (8 * 1024 * 1024)
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#define PSRAM_SIZE_16MB (16 * 1024 * 1024)
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#define PSRAM_SIZE_32MB (32 * 1024 * 1024)
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#define PSRAM_CACHE_S80M 1
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#define PSRAM_CACHE_S40M 2
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#define PSRAM_CACHE_MAX 3
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#define SPIRAM_WRAP_MODE_16B 0
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#define SPIRAM_WRAP_MODE_32B 1
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#define SPIRAM_WRAP_MODE_64B 2
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#define SPIRAM_WRAP_MODE_DISABLE 3
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/* See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the
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* definitions of these modes. Important is that NORMAL works with the app
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* CPU cache disabled, but gives huge cache coherency issues when both app
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* and pro CPU are enabled. LOWHIGH and EVENODD do not have these coherency
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* issues but cannot be used when the app CPU cache is disabled.
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*/
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#define PSRAM_VADDR_MODE_NORMAL 0 /* App and Pro CPU use their own flash
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* cache for external RAM access
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*/
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#define PSRAM_VADDR_MODE_LOWHIGH 1 /* App and Pro CPU share external RAM caches:
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* pro CPU has low 2M, app CPU has high 2M
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*/
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#define PSRAM_VADDR_MODE_EVENODD 2 /* App and Pro CPU share external RAM caches:
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* pro CPU does even 32yte ranges, app does
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* odd ones.
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*/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: psram_get_physical_size
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*
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* Description:
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* Get the physical psram size in bytes.
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*
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****************************************************************************/
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int psram_get_physical_size(uint32_t *out_size_bytes);
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/****************************************************************************
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* Name: psram_get_available_size
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*
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* Description:
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* Get the available physical psram size in bytes.
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*
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* If ECC is enabled, available PSRAM size will be 15/16 times its
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* physical size. If not, it equals to the physical psram size.
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* Note: For now ECC is only enabled on ESP32S3 Octal PSRAM
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*
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* Input Parameters:
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* out_size_bytes - availabe physical psram size in bytes.
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*
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* Returned Value:
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* 0 if success or a negative value if fail.
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*
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****************************************************************************/
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int psram_get_available_size(uint32_t *out_size_bytes);
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/****************************************************************************
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* Name: psram_get_available_size
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*
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* Description:
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* Enable psram cache
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*
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* Esp-idf uses this to initialize cache for psram, mapping it into the
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* main memory address space.
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*
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* Input Parameters:
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* mode - SPI mode to access psram in.
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* vaddrmode - Mode the psram cache works in.
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*
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* Returned Value:
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* 0 if success or a negative value if fail.
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*
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****************************************************************************/
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int psram_enable(int mode, int vaddrmode);
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/****************************************************************************
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* Name: psram_get_cs_io
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*
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* Description:
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* Get the psram CS IO
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*
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* Returned Value:
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* The psram CS IO pin.
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*
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****************************************************************************/
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uint8_t psram_get_cs_io(void);
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H */
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