Gwenhael Goavec-Merou 5ec2b9d6fe arch/arm/src/stm32/stm32f33xxx_rcc.c: A flash wait state configuration. Flash latency must be fixed according to sysclk frequency. If this operation ... is not done or done after PLL configuration, the STM32 fail to continue boot operation if the frequency if greater than 24MHz. This common t add this operation according to the board variable STM32_SYSCLK_FREQUENCY. Tested on stm32f334-disco board.		2018-02-17 12:27:29 -06:00
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include	armv7-a, armv7-r, armv7-m: Add atomic read-add-write and read-subtract-write functions.	2018-02-04 12:22:03 -06:00
src	arch/arm/src/stm32/stm32f33xxx_rcc.c: A flash wait state configuration. Flash latency must be fixed according to sysclk frequency. If this operation	2018-02-17 12:27:29 -06:00
Kconfig	spin_lock_irqsave() and spin_unlock_irqrestore() are only valid if the CPU supports global disabling of interrupts.	2018-02-04 15:41:22 -06:00