240 lines
11 KiB
C
240 lines
11 KiB
C
/************************************************************************************
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* arch/arm/src/imx1/imx_cspi.h
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*
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* Copyright (C) 2009-2010, 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_IMX_CSPI_H
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#define __ARCH_ARM_IMX_CSPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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# include <nuttx/spi/spi.h>
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* CSPI Register Offsets ************************************************************/
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#define CSPI_RXD_OFFSET 0x0000 /* Receive Data Register */
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#define CSPI_TXD_OFFSET 0x0004 /* Transmit Data Register */
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#define CSPI_CTRL_OFFSET 0x0008 /* Control Register */
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#define CSPI_INTCS_OFFSET 0x000c /* Interrupt Control/Status Register */
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#define CSPI_TEST_OFFSET 0x0010 /* Test Register */
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#define CSPI_SPCR_OFFSET 0x0014 /* Sample Period Control Register */
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#define CSPI_DMA_OFFSET 0x0018 /* DMA Control Register */
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#define CSPI_RESET_OFFSET 0x001c /* Soft Reset Register */
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/* CSPI Register Addresses **********************************************************/
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/* CSPI1 */
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#define IMX_CSPI1_RXD (IMX_CSPI1_VBASE + CSPI_RXD_OFFSET)
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#define IMX_CSPI1_TXD (IMX_CSPI1_VBASE + CSPI_TXD_OFFSET)
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#define IMX_CSPI1_CTRL (IMX_CSPI1_VBASE + CSPI_CTRL_OFFSET)
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#define IMX_CSPI1_INTCS (IMX_CSPI1_VBASE + CSPI_INTCS_OFFSET)
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#define IMX_CSPI1_SPITEST (IMX_CSPI1_VBASE + CSPI_TEST_OFFSET)
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#define IMX_CSPI1_SPISPCR (IMX_CSPI1_VBASE + CSPI_SPCR_OFFSET)
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#define IMX_CSPI1_SPIDMA (IMX_CSPI1_VBASE + CSPI_DMA_OFFSET)
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#define IMX_CSPI1_SPIRESET (IMX_CSPI1_VBASE + CSPI_RESET_OFFSET)
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/* CSPI2 */
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#define IMX_CSPI2_RXD (IMX_CSPI2_VBASE + CSPI_RXD_OFFSET)
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#define IMX_CSPI2_TXD (IMX_CSPI2_VBASE + CSPI_TXD_OFFSET)
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#define IMX_CSPI2_CTRL (IMX_CSPI2_VBASE + CSPI_CTRL_OFFSET)
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#define IMX_CSPI2_INTCS (IMX_CSPI2_VBASE + CSPI_INTCS_OFFSET)
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#define IMX_CSPI2_SPITEST (IMX_CSPI2_VBASE + CSPI_TEST_OFFSET)
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#define IMX_CSPI2_SPISPCR (IMX_CSPI2_VBASE + CSPI_SPCR_OFFSET)
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#define IMX_CSPI2_SPIDMA (IMX_CSPI2_VBASE + CSPI_DMA_OFFSET)
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#define IMX_CSPI2_SPIRESET (IMX_CSPI2_VBASE + CSPI_RESET_OFFSET)
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/* CSPI Register Bit Definitions ****************************************************/
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/* CSPI Control Register */
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#define CSPI_CTRL_DATARATE_SHIFT 13
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#define CSPI_CTRL_DATARATE_MASK (7 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV4 (0 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV8 (1 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV16 (2 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV32 (3 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV64 (4 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV128 (5 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV256 (6 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV512 (7 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DRCTL_SHIFT 11
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#define CSPI_CTRL_DRCTL_MASK (3 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_DRCTL_IGNRDY (0 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_DRCTL_FALLING (1 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_DRCTL_ACTVLOW (2 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_MODE (1 << 10)
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#define CSPI_CTRL_SPIEN (1 << 9)
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#define CSPI_CTRL_XCH (1 << 8)
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#define CSPI_CTRL_SSPOL (1 << 7)
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#define CSPI_CTRL_SSCTL (1 << 6)
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#define CSPI_CTRL_PHA (1 << 5)
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#define CSPI_CTRL_POL (1 << 4)
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#define CSPI_CTRL_BITCOUNT_SHIFT 0
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#define CSPI_CTRL_BITCOUNT_MASK (15 << CSPI_CTRL_BITCOUNT_SHIFT)
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/* CSPI Interrupt Control/Status Register */
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#define CSPI_INTCS_TE (1 << 0) /* Bit 0: TXFIFO Empty Status */
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#define CSPI_INTCS_TH (1 << 1) /* Bit 1: TXFIFO Half Status */
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#define CSPI_INTCS_TF (1 << 2) /* Bit 2: TXFIFO Full Status */
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#define CSPI_INTCS_RR (1 << 3) /* Bit 3: RXFIFO Data Ready Status */
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#define CSPI_INTCS_RH (1 << 4) /* Bit 4: RXFIFO Half Status */
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#define CSPI_INTCS_RF (1 << 5) /* Bit 5: RXFIFO Full Status */
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#define CSPI_INTCS_RO (1 << 6) /* Bit 6: RXFIFO Overflow */
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#define CSPI_INTCS_BO (1 << 7) /* Bit 7: Bit Count Overflow */
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#define CSPI_INTCS_TEEN (1 << 8) /* Bit 8: TXFIFO Empty Interrupt Enable */
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#define CSPI_INTCS_THEN (1 << 9) /* Bit 9: TXFIFO Half Interrupt Enable */
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#define CSPI_INTCS_TFEN (1 << 10) /* Bit 10: TXFIFO Full Interrupt Enable */
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#define CSPI_INTCS_RREN (1 << 11) /* Bit 11: RXFIFO Data Ready Interrupt Enable */
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#define CSPI_INTCS_RHEN (1 << 12) /* Bit 12: RXFIFO Half Interrupt Enable */
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#define CSPI_INTCS_RFEN (1 << 13) /* Bit 13: RXFIFO Full Interrupt Enable */
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#define CSPI_INTCS_ROEN (1 << 14) /* BIT 14: RXFIFO Overflow Interrupt Enable */
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#define CSPI_INTCS_BOEN (1 << 15) /* Bit 15: Bit Count Overflow Interrupt Enable */
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#define CSPI_INTCS_ALLINTS 0x0000ff00
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/* CSPI Sample Period Control Register */
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#define CSPI_SPCR_WAIT_SHIFT 0
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#define CSPI_SPCR_WAIT_MASK (0x7ff << CSPI_SPCR_WAIT_SHIFT)
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#define CSPI_SPCR_CSRC (1 << 15) /* Bit 15: 1:32768 or 32 kHz clock source */
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/* CSPI DMA Control Register */
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#define CSPI_DMA_RHDMA (1 << 4) /* Bit 4: RXFIFO Half Status */
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#define CSPI_DMA_RFDMA (1 << 5) /* Bit 5: RXFIFO Full Status */
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#define CSPI_DMA_TEDMA (1 << 6) /* Bit 6: TXFIFO Empty Status */
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#define CSPI_DMA_THDMA (1 << 7) /* Bit 7: TXFIFO Half Status */
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#define CSPI_DMA_RHDEN (1 << 12) /* Bit 12: Enable RXFIFO Half DMA Request */
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#define CSPI_DMA_RFDEN (1 << 13) /* Bit 13: Enables RXFIFO Full DMA Request */
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#define CSPI_DMA_TEDEN (1 << 14) /* Bit 14: Enable TXFIFO Empty DMA Request */
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#define CSPI_DMA_THDEN (1 << 15) /* Bit 15: Enable TXFIFO Half DMA Request */
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/* Soft Reset Register */
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#define CSPI_RESET_START (1 << 0) /* Bit 0: Execute soft reset */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif /* __cplusplus */
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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struct spi_dev_s; /* Forward reference */
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/****************************************************************************
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* Name: imx_spibus_initialize
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*
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* Description:
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* Initialize common parts the selected SPI port. Initialization of
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* chip select GPIOs must have been performed by board specific logic
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* prior to calling this function. Specifically: GPIOs should have
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* been configured for output, and all chip selects disabled.
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*
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* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
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* If multiple devices on on the bus, then multiple chip selects will be
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* required. Therefore, all GPIO chip management is deferred to board-
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* specific logic.
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*
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* Input Parameters:
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* Port number (for hardware that has multiple SPI interfaces)
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*
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* Returned Value:
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* Valid SPI device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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FAR struct spi_dev_s *imx_spibus_initialize(int port);
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/****************************************************************************
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* The external functions, imx_spiselect, imx_spistatus, and imx_cmddaa must be
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* provided by board-specific logic. These are implementations of the select and
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* status methods of the SPI interface defined by struct spi_ops_s (see
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* include/nuttx/spi/spi.h). All other methods (including imx_spibus_initialize()) are
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* provided by common logic. To use this common SPI logic on your board:
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*
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* 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific
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* logic. This function will perform chip selection and status operations using
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* GPIOs in the way your board is configured.
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* 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the
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* imx_spicmddata() function in your board-specific logic. This function will
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* perform cmd/data selection operations using GPIOs in the way your board is
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* configured.
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* 3. Add a call to imx_spibus_initialize() in your low level initialization logic
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* 4. The handle returned by imx_spibus_initialize() may then be used to bind the
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* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
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* for example, will bind the SPI driver to the SPI MMC/SD driver).
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*
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****************************************************************************/
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void imx_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
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uint8_t imx_spistatus(FAR struct spi_dev_s *dev, uint32_t devid);
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#ifdef CONFIG_SPI_CMDDATA
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int imx_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_IMX_CSPI_H */
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