Tiago Medicci Serrano 0ddb64555a esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation ... This commit provides an interface to register ISRs that run from IRAM and keeps track of the non-IRAM interrupts. It enables, for instance, to avoid disabling all the interrupts during a SPI flash operation: IRAM-enabled ISRs are, then, able to run during these operations.		2023-10-05 11:25:43 +08:00
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chip.h
core-isa.h	libc/machine/xtensa: make longjmp safe against context switch	2022-11-22 19:34:44 +01:00
irq.h	esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation	2023-10-05 11:25:43 +08:00
tie-asm.h
tie.h