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614570cdcb
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Lee Lup Yuen 614570cdcb arch/riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906) 
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.

Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64

`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC

`include/bl808/chip.h`: BL808 Definitions

`include/bl808/irq.h`: External Interrupts

`src/bl808/chip.h`: Interrupt Stack Macro

`src/bl808/bl808_allocateheap.c`: Kernel Heap

`src/bl808/bl808_head.S`: Linux Header and Boot Code

`src/bl808/bl808_irq.c`: Configure Interrupts

`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts

`src/bl808/bl808_memorymap.h`: Memory Map

`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt

`src/bl808/bl808_pgalloc.c`: Page Allocator

`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver

`src/bl808/bl808_start.c`: Startup Code

`src/bl808/bl808_timerisr.c`: Timer Interrupt

`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address

`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses

`src/bl808/hardware/bl808_uart.h`: UART Register Addresses

`src/bl808/Kconfig`: BL808 Config

`src/bl808/Make.defs`: Makefile
2023-12-12 08:50:03 -08:00
..
include arch/riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906) 2023-12-12 08:50:03 -08:00
src arch/riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906) 2023-12-12 08:50:03 -08:00
CMakeLists.txt cmake:init RISC-V cmake qemu-rv build 2023-10-26 21:01:46 +08:00
Kconfig arch/riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906) 2023-12-12 08:50:03 -08:00