c7e9f20845
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4427 42af7a65-404d-4744-a932-0658087f49c3
287 lines
9.7 KiB
ArmAsm
287 lines
9.7 KiB
ArmAsm
/************************************************************************************
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* arch/arm/src/armv7-m/stm32_fpu.S
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*
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/*
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* When this file is assembled, it will require the following GCC options:
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*
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* -mcpu=cortex-m3 -mfloat-abi=hard -mfpu=vfp -meabi=5
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*/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#ifdef CONFIG_ARCH_FPU
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/************************************************************************************
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* Preprocessor Definitions
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************************************************************************************/
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/************************************************************************************
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* Global Symbols
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************************************************************************************/
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.globl up_savefpu
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.globl up_restorefpu
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.syntax unified
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.thumb
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.file "up_fpu.S"
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: up_savefpu
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*
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* Description:
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* Given the pointer to a register save area (in R0), save the state of the
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* floating point registers.
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*
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* C Function Prototype:
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* void up_savefpu(uint32_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area in which to save the floating point
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* registers
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.thumb_func
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.type up_savefpu, function
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up_savefpu:
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add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
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/* Some older GNU assemblers don't support all the newer UAL mnemonics. */
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#if 1 /* Use UAL mnemonics */
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/* Store all floating point registers. Registers are stored in numeric order,
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* s0, s1, ... in increasing address order.
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*/
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vstmia r1!, {s0-s31} /* Save the full FP context */
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/* Store the floating point control and status register. At the end of the
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* vstmia, r1 will point to the FPCSR storage location.
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*/
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vmrs r2, fpscr /* Fetch the FPCSR */
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str r2, [r1], #4 /* Save the floating point control and status register */
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#else
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/* Store all floating point registers */
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#if 1 /* Use store multiple */
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fstmias r1!, {s0-s31} /* Save the full FP context */
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#else
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vmov r2, r3, d0 /* r2, r3 = d0 */
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str r2, [r1], #4 /* Save S0 and S1 values */
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str r3, [r1], #4
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vmov r2, r3, d1 /* r2, r3 = d1 */
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str r2, [r1], #4 /* Save S2 and S3 values */
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str r3, [r1], #4
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vmov r2, r3, d2 /* r2, r3 = d2 */
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str r2, [r1], #4 /* Save S4 and S5 values */
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str r3, [r1], #4
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vmov r2, r3, d3 /* r2, r3 = d3 */
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str r2, [r1], #4 /* Save S6 and S7 values */
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str r3, [r1], #4
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vmov r2, r3, d4 /* r2, r3 = d4 */
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str r2, [r1], #4 /* Save S8 and S9 values */
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str r3, [r1], #4
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vmov r2, r3, d5 /* r2, r3 = d5 */
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str r2, [r1], #4 /* Save S10 and S11 values */
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str r3, [r1], #4
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vmov r2, r3, d6 /* r2, r3 = d6 */
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str r2, [r1], #4 /* Save S12 and S13 values */
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str r3, [r1], #4
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vmov r2, r3, d7 /* r2, r3 = d7 */
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str r2, [r1], #4 /* Save S14 and S15 values */
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str r3, [r1], #4
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vmov r2, r3, d8 /* r2, r3 = d8 */
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str r2, [r1], #4 /* Save S16 and S17 values */
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str r3, [r1], #4
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vmov r2, r3, d9 /* r2, r3 = d9 */
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str r2, [r1], #4 /* Save S18 and S19 values */
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str r3, [r1], #4
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vmov r2, r3, d10 /* r2, r3 = d10 */
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str r2, [r1], #4 /* Save S20 and S21 values */
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str r3, [r1], #4
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vmov r2, r3, d11 /* r2, r3 = d11 */
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str r2, [r1], #4 /* Save S22 and S23 values */
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str r3, [r1], #4
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vmov r2, r3, d12 /* r2, r3 = d12 */
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str r2, [r1], #4 /* Save S24 and S25 values */
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str r3, [r1], #4
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vmov r2, r3, d13 /* r2, r3 = d13 */
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str r2, [r1], #4 /* Save S26 and S27 values */
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str r3, [r1], #4
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vmov r2, r3, d14 /* r2, r3 = d14 */
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str r2, [r1], #4 /* Save S28 and S29 values */
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str r3, [r1], #4
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vmov r2, r3, d15 /* r2, r3 = d15 */
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str r2, [r1], #4 /* Save S30 and S31 values */
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str r3, [r1], #4
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#endif
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/* Store the floating point control and status register */
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fmrx r2, fpscr /* Fetch the FPCSR */
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str r2, [r1], #4 /* Save the floating point control and status register */
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#endif
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bx lr
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.size up_savefpu, .-up_savefpu
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/************************************************************************************
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* Name: up_restorefpu
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*
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* Description:
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* Given the pointer to a register save area (in R0), restore the state of the
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* floating point registers.
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*
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* C Function Prototype:
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* void up_restorefpu(const uint32_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area containing the floating point
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* registers.
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*
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* Returned Value:
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* This function does not return anything explicitly. However, it is called from
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* interrupt level assembly logic that assumes that r0 is preserved.
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*
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************************************************************************************/
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.thumb_func
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.type up_restorefpu, function
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up_restorefpu:
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add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
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/* Some older GNU assemblers don't support all the newer UAL mnemonics. */
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#if 1 /* Use UAL mnemonics */
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/* Load all floating point registers. Registers are loaded in numeric order,
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* s0, s1, ... in increasing address order.
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*/
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vldmia r1!, {s0-s31} /* Restore the full FP context */
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/* Load the floating point control and status register. At the end of the
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* vstmia, r1 will point to the FPCSR storage location.
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*/
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ldr r2, [r1], #4 /* Fetch the floating point control and status register */
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vmsr fpscr, r2 /* Restore the FPCSR */
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#else
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/* Load all floating point registers Registers are loaded in numeric order,
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* s0, s1, ... in increasing address order.
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*/
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#if 1 /* Use load multiple */
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fldmias r1!, {s0-s31} /* Restore the full FP context */
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#else
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ldr r2, [r1], #4 /* Fetch S0 and S1 values */
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ldr r3, [r1], #4
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vmov d0, r2, r3 /* Save as d0 */
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ldr r2, [r1], #4 /* Fetch S2 and S3 values */
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ldr r3, [r1], #4
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vmov d1, r2, r3 /* Save as d1 */
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ldr r2, [r1], #4 /* Fetch S4 and S5 values */
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ldr r3, [r1], #4
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vmov d2, r2, r3 /* Save as d2 */
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ldr r2, [r1], #4 /* Fetch S6 and S7 values */
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ldr r3, [r1], #4
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vmov d3, r2, r3 /* Save as d3 */
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ldr r2, [r1], #4 /* Fetch S8 and S9 values */
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ldr r3, [r1], #4
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vmov d4, r2, r3 /* Save as d4 */
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ldr r2, [r1], #4 /* Fetch S10 and S11 values */
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ldr r3, [r1], #4
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vmov d5, r2, r3 /* Save as d5 */
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ldr r2, [r1], #4 /* Fetch S12 and S13 values */
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ldr r3, [r1], #4
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vmov d6, r2, r3 /* Save as d6 */
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ldr r2, [r1], #4 /* Fetch S14 and S15 values */
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ldr r3, [r1], #4
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vmov d7, r2, r3 /* Save as d7 */
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ldr r2, [r1], #4 /* Fetch S16 and S17 values */
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ldr r3, [r1], #4
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vmov d8, r2, r3 /* Save as d8 */
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ldr r2, [r1], #4 /* Fetch S18 and S19 values */
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ldr r3, [r1], #4
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vmov d9, r2, r3 /* Save as d9 */
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ldr r2, [r1], #4 /* Fetch S20 and S21 values */
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ldr r3, [r1], #4
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vmov d10, r2, r3 /* Save as d10 */
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ldr r2, [r1], #4 /* Fetch S22 and S23 values */
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ldr r3, [r1], #4
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vmov d11, r2, r3 /* Save as d11 */
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ldr r2, [r1], #4 /* Fetch S24 and S25 values */
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ldr r3, [r1], #4
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vmov d12, r2, r3 /* Save as d12 */
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ldr r2, [r1], #4 /* Fetch S26 and S27 values */
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ldr r3, [r1], #4
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vmov d13, r2, r3 /* Save as d13 */
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ldr r2, [r1], #4 /* Fetch S28 and S29 values */
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ldr r3, [r1], #4
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vmov d14, r2, r3 /* Save as d14 */
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ldr r2, [r1], #4 /* Fetch S30 and S31 values */
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ldr r3, [r1], #4
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vmov d15, r2, r3 /* Save as d15 */
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#endif
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/* Load the floating point control and status register. r1 points t
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* the address of the FPCSR register.
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*/
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ldr r2, [r1], #4 /* Fetch the floating point control and status register */
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fmxr fpscr, r2 /* Restore the FPCSR */
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#endif
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bx lr
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.size up_restorefpu, .-up_restorefpu
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#endif /* CONFIG_ARCH_FPU */
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.end
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