249 lines
8.7 KiB
C
249 lines
8.7 KiB
C
/****************************************************************************
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* boards/arm/stm32/mikroe-stm32f4/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32_sdio.h"
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#include "stm32.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The Mikroe STM32F4 Mikromedia board features a single 32kHz crystal.
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* The main clock uses the internal 16Mhz RC oscillator.
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*
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* This is the canonical configuration:
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* System Clock source :PLL (HSE)
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* SYSCLK(Hz) :168000000 Determined by PLL configuration
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* HCLK(Hz) :168000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler :1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler :4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler :2 (STM32_RCC_CFGR_PPRE2)
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* HSI Frequency(Hz) :16000000 (STM32_HSI_FREQUENCY)
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* PLLM :16 (STM32_PLLCFG_PLLM)
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* PLLN :36 (STM32_PLLCFG_PLLN)
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* PLLP :2 (STM32_PLLCFG_PLLP)
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* PLLQ :7 (STM32_PLLCFG_PLLQ)
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* Main regulator output voltage :Scale1 mode Needed for high speed SYSCLK
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* Flash Latency(WS) :5
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* Prefetch Buffer :OFF
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* Instruction cache :ON
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* Data cache :ON
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* Require 48MHz for USB OTG FS, :Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 8MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSI
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* PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN
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* = (16,000,000 / 16) * 336
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 2 = 168,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* LED definitions **********************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
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* any way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#if 0
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_LED4 3
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#endif
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#define BOARD_NLEDS 0
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#if 0
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_ORANGE BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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#define BOARD_LED_BLUE BOARD_LED4
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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#define BOARD_LED4_BIT (1 << BOARD_LED4)
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/* If CONFIG_ARCH_LEDs is defined,
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* then NuttX will control the 4 LEDs on board the stm32f4discovery.
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* The following definitions describe how NuttX controls the LEDs:
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*/
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#define LED_STARTED 0 /* LED1 */
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#define LED_HEAPALLOCATE 1 /* LED2 */
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#define LED_IRQSENABLED 2 /* LED1 + LED2 */
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#define LED_STACKCREATED 3 /* LED3 */
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#define LED_INIRQ 4 /* LED1 + LED3 */
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#define LED_SIGNAL 5 /* LED2 + LED3 */
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#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
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#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
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/* Button definitions *******************************************************/
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/* The STM32F4 Discovery supports one button: */
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#define BUTTON_USER 0
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#define NUM_BUTTONS 0
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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#endif /* 0 */
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/* Alternate function pin selections ****************************************/
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/* UART2:
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*
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* The Mikroe-STM32F4 board has no on-board serial devices, but it brings out
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* UART2 to the expansion header.
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* (See the README.txt file for other options)
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_2
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#define GPIO_USART2_TX GPIO_USART2_TX_2
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/* PWM
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*
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* The STM32F4 Discovery has no real on-board PWM devices, but the board can
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* be configured to output a pulse train using TIM4 CH2 on PD13.
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*/
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#define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2
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/* SPI - Onboard devices use SPI3, plus SPI2 routes to the I/O header */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2
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#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX
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#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_2
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_2
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#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_2
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#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_2
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/* Timer Inputs/Outputs (see the README.txt file for options) */
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#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_2
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#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1
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#define GPIO_TIM8_CH1IN GPIO_TIM8_CH1IN_1
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#define GPIO_TIM8_CH2IN GPIO_TIM8_CH2IN_1
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#endif /* __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H */
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