Xiang Xiao 629d9969dd arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall ...

follow other function naming(e.g. riscv_dispatch_irq)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

2022-04-02 14:08:37 +03:00

..

bl602

arch/risc-v: Remove dupped irq code from bl602

2022-01-21 00:44:43 +08:00

c906

arch/risc-v: Remove dupped irq code from c906

2022-01-21 00:44:43 +08:00

esp32c3

…

fe310

arch/risc-v: Remove dupped irq code from fe310

2022-01-21 00:44:43 +08:00

k210

arch/risc-v: Remove dupped irq code from k210

2022-01-21 00:44:43 +08:00

litex

arch/risc-v/src/litex/litex_sdio: add litesdcard peripheral driver

2022-03-30 02:35:27 +08:00

mpfs

arch/risc-v: Remove dupped irq code from mpfs

2022-01-21 00:44:43 +08:00

qemu-rv

arch/risc-v: Remove dupped irq code from qemu-rv

2022-01-21 00:44:43 +08:00

rv32m1

arch/risc-v: Merge mcause.h into irq.h

2022-01-22 14:57:05 +08:00

.gitignore

…

arch.h

arch/risc-v: get wider visibility for arch instruction macros

2022-04-01 10:31:24 +08:00

barriers.h

RISC-V: Add common data memory and instruction barriers

2022-03-18 18:20:12 +08:00

csr.h

arch/riscv: Align the macro definition in csr.h

2022-04-02 14:08:37 +03:00

elf.h

…

inttypes.h

arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64

2022-01-04 23:22:43 +08:00

irq.h

RISC-V: Implement option to run NuttX in supervisor mode (S-mode)

2022-04-01 16:19:42 -03:00

limits.h

arch/risc-v: Refine Toolchain.defs

2021-12-28 00:30:10 -06:00

mode.h

RISC-V: Implement option to run NuttX in supervisor mode (S-mode)

2022-04-01 16:19:42 -03:00

setjmp.h

arch/risc-v: Save/Load float register in setjmp

2022-03-09 10:15:54 +02:00

spinlock.h

arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64

2022-01-04 23:22:43 +08:00

stdarg.h

…

syscall.h

arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall

2022-04-02 14:08:37 +03:00

types.h

arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64

2022-01-04 23:22:43 +08:00