63364a52ff
Whenever a SPI flash operation is going to take place, it's necessary to disable both the instruction and data cache. In order to avoid the other CPU (if SMP is enabled) to retrieve data from the SPI flash, it needs to be paused until the current SPI flash operation finishes. All the code that "pauses" the other CPU (in fact, the CPU spins until `up_cpu_resume` is called) needs to run from the instruction RAM. |
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| .. | ||
| .gitignore | ||
| esp32s3_peripherals.ld | ||
| esp32s3_rom.ld | ||
| flat_memory.ld | ||
| kernel-space.ld | ||
| legacy_sections.ld | ||
| mcuboot_sections.ld | ||
| protected_memory.ld | ||
| user-space.ld | ||