337 lines
16 KiB
C
337 lines
16 KiB
C
/************************************************************************************
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* arch/renesas/include/m16c/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_RENESAS_INCLUDE_M16C_IRQ_H
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#define __ARCH_RENESAS_INCLUDE_M16C_IRQ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* IRQ numbers **********************************************************************/
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/* Fixed vector table */
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#define M16C_UNDEFINST_IRQ 0 /* fffdc: Undefined instruction */
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#define M16C_OVERFLOW_IRQ 1 /* fffe0: Overflow */
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#define M16C_BRK_IRQ 2 /* fffe4: BRK instruction */
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#define M16C_ADDRMATCH_IRQ 3 /* fffe8: Address match */
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#ifdef CONFIG_M16C_DEBUGGER
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# define M16C_SSTEP_IRQ 4 /* fffec: Single step */
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# define M16C_WDOG_IRQ 5 /* ffff0: Watchdog timer */
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# define M16C_DBC_IRQ 6 /* ffff4: DBC */
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# define M16C_NMI_IRQ 7 /* ffff8: NMI */
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# define _LAST_FIXED 7
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#else
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# define M16C_WDOG_IRQ 4 /* ffff0: Watchdog timer */
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# define M16C_NMI_IRQ 5 /* ffff8: NMI */
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# define _LAST_FIXED 5
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#endif
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/* Variable vector table (fixed at address 0xffd00) */
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#ifdef CONFIG_M16C_SWINTS
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# define M16C_BRK_IRQ (_LAST_FIXED+1) /* ffd00: BRK instruction */
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# define M16C_SWINT0_IRQ M16C_BRK_IRQ /* S/W interrupt 0 */
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# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
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# define M16C_SWINT4_IRQ M16C_INT3_IRQ /* S/W interrupt 4 */
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# define M16C_CTXSV_SWINT (_LAST_FIXED+3) /* ffd14: Reserved -- used by NuttX */
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# define M16C_SWINT5_IRQ M16C_CTXSV_SWINT /* S/W interrupt 5 */
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# define M16C_SWINT6_IRQ (_LAST_FIXED+4) /* ffd18: Reserved / S/W interrupt 6 */
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# define M16C_SWINT7_IRQ (_LAST_FIXED+5) /* ffd1c: Reserved / S/W interrupt 7 */
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# define M16C_INT5_IRQ (_LAST_FIXED+6) /* ffd20: INT5 */
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# define M16C_SWINT8_IRQ M16C_INT5_IRQ /* S/W interrupt 8 */
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# define M16C_INT4_IRQ (_LAST_FIXED+7) /* ffd24: INT4 */
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# define M16C_SWINT9_IRQ M16C_INT4_IRQ /* S/W interrupt 9 */
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# define M16C_UART2BCD_IRQ (_LAST_FIXED+8) /* ffd28: UART2 bus collision detection */
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# define M16C_SWINT10_IRQ M16C_UART2BCD_IRQ /* S/W interrupt 10 */
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# define M16C_DMA0_IRQ (_LAST_FIXED+9) /* ffd2c: DMA0 */
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# define M16C_SWINT11_IRQ M16C_DMA0_IRQ /* S/W interrupt 11 */
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# define M16C_DMA1_IRQ (_LAST_FIXED+10) /* ffd30: DMA1 */
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# define M16C_SWINT12_IRQ M16C_DMA1_IRQ /* S/W interrupt 12 */
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# define M16C_KEYINP_IRQ (_LAST_FIXED+11) /* ffd34: Key input interrupt */
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# define M16C_SWINT13_IRQ M16C_KEYINP_IRQ /* S/W interrupt 13 */
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# define M16C_ADC_IRQ (_LAST_FIXED+12) /* ffd38: A-D */
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# define M16C_SWINT14_IRQ M16C_ADC_IRQ /* S/W interrupt 14 */
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# define M16C_UARTXNAK_IRQ (_LAST_FIXED+13) /* ffd3c UART2 transmit/NACK2 */
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# define M16C_SWINT15_IRQ M16C_UARTNAK_IRQ /* S/W interrupt 15 */
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# define M16C_UARTRACK_IRQ (_LAST_FIXED+14) /* ffd40: UART2 receive/ACK2 */
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# define M16C_SWINT16_IRQ M16C_UARTRACK_IRQ /* S/W interrupt 16 */
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# define M16C_UART0XMT_IRQ (_LAST_FIXED+15) /* ffd44: UART0 transmit */
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# define M16C_SWINT17_IRQ M16C_UART0XMT_IRQ /* S/W interrupt 17 */
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# define M16C_UART0RCV_IRQ (_LAST_FIXED+16) /* ffd48: UART0 receive */
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# define M16C_SWINT18_IRQ M16C_UART0RCV_IRQ /* S/W interrupt 18 */
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# define M16C_UART1XMT_IRQ (_LAST_FIXED+17) /* ffd4c: UART1 transmit */
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# define M16C_SWINT19_IRQ M16C_UART1XMT_IRQ /* S/W interrupt 19 */
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# define M16C_UART1RCV_IRQ (_LAST_FIXED+18) /* ffd50: UART1 receive */
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# define M16C_SWINT20_IRQ M16C_UART1RCV_IRQ /* S/W interrupt 20 */
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# define M16C_TMRA0_IRQ (_LAST_FIXED+19) /* ffd54: Timer A0 */
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# define M16C_SWINT21_IRQ M16C_TMRA0_IRQ /* S/W interrupt 21 */
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# define M16C_TMRA1_IRQ (_LAST_FIXED+20) /* ffd58: Timer A1 */
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# define M16C_SWINT22_IRQ M16C_TMRA1_IRQ /* S/W interrupt 22 */
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# define M16C_TMRA2_IRQ (_LAST_FIXED+21) /* ffd5c: Timer A2 */
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# define M16C_SWINT23_IRQ M16C_TMRA2_IRQ /* S/W interrupt 23 */
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# define M16C_TMRA3_IRQ (_LAST_FIXED+22) /* ffd60: Timer A3 */
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# define M16C_SWINT24_IRQ M16C_TMRA3_IRQ /* S/W interrupt 24 */
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# define M16C_TMRA4_IRQ (_LAST_FIXED+23) /* ffd64: Timer A4 */
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# define M16C_SWINT25_IRQ M16C_TMRA4_IRQ /* S/W interrupt 25 */
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# define M16C_TMRB0_IRQ (_LAST_FIXED+24) /* ffd68: Timer B0 */
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# define M16C_SWINT26_IRQ M16C_TMRB0_IRQ /* S/W interrupt 26 */
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# define M16C_TMRB1_IRQ (_LAST_FIXED+25) /* ffd6c: Timer B1 */
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# define M16C_SWINT27_IRQ M16C_TMRB1_IRQ /* S/W interrupt 27 */
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# define M16C_TMRB2_IRQ (_LAST_FIXED+26) /* ffd70: Timer B2 */
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# define M16C_SWINT28_IRQ M16C_TMRB2_IRQ /* S/W interrupt 28 */
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# define M16C_INT0_IRQ (_LAST_FIXED+27) /* ffd74: INT0 */
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# define M16C_SWINT29_IRQ M16C_INT0_IRQ /* S/W interrupt 29 */
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# define M16C_INT1_IRQ (_LAST_FIXED+28) /* ffd78: INT1 */
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# define M16C_SWINT30_IRQ M16C_INT1_IRQ /* S/W interrupt 30 */
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# define M16C_SWINT31_IRQ (_LAST_FIXED+29) /* ffd7c: Reserved / S/W interrupt 31 */
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# define M16C_CTXRSTR_SWINT (_LAST_FIXED+30) /* ffd80: Used by NuttX */
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# define M16C_SWINT32IRQ M16C_CTXRSTR_SWINT /* S/W interrupt 32 */
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# define M16C_SWINT33_IRQ (_LAST_FIXED+31) /* ffd84: S/W interrupt 33 */
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# define M16C_SWINT34_IRQ (_LAST_FIXED+32) /* ffd88: S/W interrupt 34 */
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# define M16C_SWINT35_IRQ (_LAST_FIXED+33) /* ffd8c: S/W interrupt 35 */
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# define M16C_SWINT36_IRQ (_LAST_FIXED+34) /* ffd90: S/W interrupt 36 */
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# define M16C_SWINT37_IRQ (_LAST_FIXED+35) /* ffd94: S/W interrupt 37 */
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# define M16C_SWINT38_IRQ (_LAST_FIXED+36) /* ffd98: S/W interrupt 38 */
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# define M16C_SWINT39_IRQ (_LAST_FIXED+37) /* ffd9c: S/W interrupt 39 */
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# define M16C_SWINT40_IRQ (_LAST_FIXED+38) /* ffda0: S/W interrupt 40 */
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# define M16C_SWINT41_IRQ (_LAST_FIXED+39) /* ffda4: S/W interrupt 41 */
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# define M16C_SWINT42_IRQ (_LAST_FIXED+40) /* ffda8: S/W interrupt 42 */
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# define M16C_SWINT43_IRQ (_LAST_FIXED+41) /* ffdac: S/W interrupt 43 */
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# define M16C_SWINT44_IRQ (_LAST_FIXED+42) /* ffdb0: S/W interrupt 44 */
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# define M16C_SWINT45_IRQ (_LAST_FIXED+43) /* ffdb4: S/W interrupt 45 */
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# define M16C_SWINT46_IRQ (_LAST_FIXED+44) /* ffdb8: S/W interrupt 46 */
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# define M16C_SWINT47_IRQ (_LAST_FIXED+45) /* ffdbc: S/W interrupt 47 */
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# define M16C_SWINT48_IRQ (_LAST_FIXED+46) /* ffdc0: S/W interrupt 48 */
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# define M16C_SWINT49_IRQ (_LAST_FIXED+47) /* ffdc4: S/W interrupt 49 */
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# define M16C_SWINT50_IRQ (_LAST_FIXED+48) /* ffdc8: S/W interrupt 50 */
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# define M16C_SWINT51_IRQ (_LAST_FIXED+49) /* ffdcc: S/W interrupt 51 */
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# define M16C_SWINT52_IRQ (_LAST_FIXED+50) /* ffdd0: S/W interrupt 52 */
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# define M16C_SWINT53_IRQ (_LAST_FIXED+51) /* ffdd4: S/W interrupt 53 */
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# define M16C_SWINT54_IRQ (_LAST_FIXED+52) /* ffdd8: S/W interrupt 54 */
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# define M16C_SWINT55_IRQ (_LAST_FIXED+53) /* ffddc: S/W interrupt 55 */
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# define M16C_SWINT56_IRQ (_LAST_FIXED+54) /* ffde0: S/W interrupt 56 */
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# define M16C_SWINT57_IRQ (_LAST_FIXED+55) /* ffde4: S/W interrupt 57 */
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# define M16C_SWINT58_IRQ (_LAST_FIXED+56) /* ffde8: S/W interrupt 58 */
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# define M16C_SWINT59_IRQ (_LAST_FIXED+57) /* ffdec: S/W interrupt 59 */
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# define M16C_SWINT60_IRQ (_LAST_FIXED+58) /* ffdf0: S/W interrupt 60 */
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# define M16C_SWINT61_IRQ (_LAST_FIXED+59) /* ffdf4: S/W interrupt 61 */
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# define M16C_SWINT62_IRQ (_LAST_FIXED+60) /* ffdf8: S/W interrupt 62 */
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# define M16C_SWINT63_IRQ (_LAST_FIXED+61) /* ffdfc: S/W interrupt 63 */
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# define NR_IRQS (_LAST_FIXED+62) /* Total number of supported IRQs */
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#else
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# define M16C_BRK_IRQ (_LAST_FIXED+1) /* ffd00: BRK instruction */
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# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
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# define M16C_CTXSV_SWINT (_LAST_FIXED+3) /* ffd14: Reserved -- SWINT5 used by NuttX */
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# define M16C_INT5_IRQ (_LAST_FIXED+5) /* ffd20: INT5 */
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# define M16C_INT4_IRQ (_LAST_FIXED+6) /* ffd24: INT4 */
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# define M16C_UART2BCD_IRQ (_LAST_FIXED+7) /* ffd28: UART2 bus collision detection */
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# define M16C_DMA0_IRQ (_LAST_FIXED+8) /* ffd2c: DMA0 */
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# define M16C_DMA1_IRQ (_LAST_FIXED+9) /* ffd30: DMA1 */
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# define M16C_KEYINP_IRQ (_LAST_FIXED+10) /* ffd34: Key input interrupt */
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# define M16C_ADC_IRQ (_LAST_FIXED+11) /* ffd38: A-D */
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# define M16C_UARTXNAK_IRQ (_LAST_FIXED+12) /* ffd3c UART2 transmit/NACK2 */
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# define M16C_UARTRACK_IRQ (_LAST_FIXED+13) /* ffd40: UART2 receive/ACK2 */
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# define M16C_UART0XMT_IRQ (_LAST_FIXED+14) /* ffd44: UART0 transmit */
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# define M16C_UART0RCV_IRQ (_LAST_FIXED+15) /* ffd48: UART0 receive */
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# define M16C_UART1XMT_IRQ (_LAST_FIXED+16) /* ffd4c: UART1 transmit */
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# define M16C_UART1RCV_IRQ (_LAST_FIXED+17) /* ffd50: UART1 receive */
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# define M16C_TMRA0_IRQ (_LAST_FIXED+18) /* ffd54: Timer A0 */
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# define M16C_TMRA1_IRQ (_LAST_FIXED+19) /* ffd58: Timer A1 */
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# define M16C_TMRA2_IRQ (_LAST_FIXED+20) /* ffd5c: Timer A2 */
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# define M16C_TMRA3_IRQ (_LAST_FIXED+21) /* ffd60: Timer A3 */
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# define M16C_TMRA4_IRQ (_LAST_FIXED+22) /* ffd64: Timer A4 */
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# define M16C_TMRB0_IRQ (_LAST_FIXED+23) /* ffd68: Timer B0 */
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# define M16C_TMRB1_IRQ (_LAST_FIXED+24) /* ffd6c: Timer B1 */
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# define M16C_TMRB2_IRQ (_LAST_FIXED+25) /* ffd70: Timer B2 */
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# define M16C_INT0_IRQ (_LAST_FIXED+26) /* ffd74: INT0 */
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# define M16C_INT1_IRQ (_LAST_FIXED+27) /* ffd78: INT1 */
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# define M16C_CTXRSTR_SWINT (_LAST_FIXED+4) /* ffd80: S/W interrupt 32, used by NuttX */
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# define NR_IRQS (_LAST_FIXED+28) /* Total number of supported IRQs */
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#endif
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/* Timer A0 is the system timer used by NuttX */
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#define M16C_SYSTIMER_IRQ M16C_TMRA0_IRQ
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/* IRQ Stack Frame Format. The M16C has a push down stack. The CPU performs
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* the following actions when an interrupt is taken:
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*
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* - Save FLG register
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* - Clear I, D, and U flags in FLG register
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* - Builds stack frame like:
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*
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* sp -> PC bits 0-7
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* sp+1 -> PC bits 8-15
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* sp+2 -> FLG bits 0-7
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* sp+3 -> FLG (Bits 12-14) + PC (bits 16-19)
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*
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* - Sets IPL
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* - Vectors to interrupt handler
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*/
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#define REG_FLGPCHI 0 /* 8-bit FLG (bits 12-14) + PC (bits 16-19) as would be
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* presented by an interrupt */
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#define REG_FLG 1 /* 8-bit FLG register (bits 0-7) */
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#define REG_PC 2 /* 16-bit PC [0]:bits8-15 [1]:bits 0-7 */
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#define REG_FB 4 /* 16-bit FB register */
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#define REG_SB 6 /* 16-bit SB register */
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#define REG_A1 8 /* 16-bit A1 register */
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#define REG_A0 10 /* 16-bit A0 register */
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#define REG_R3 12 /* 16-bit R3 register */
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#define REG_R2 14 /* 16-bit R2 register */
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#define REG_R1 16 /* 16-bit R1 register */
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#define REG_R0 18 /* 16-bit R0 register */
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#define REG_SP 20 /* 16-bit user stack pointer */
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#define XCPTCONTEXT_SIZE 22
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* This struct defines the way the registers are stored. We need to save: */
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there are pending signals
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* to be processed.
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*/
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of LR and SR used during signal processing.
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*
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* REVISIT: Because there is only one copy of these save areas,
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* only a single signal handler can be active. This precludes
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* queuing of signal actions. As a result, signals received while
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* another signal handler is executing will be ignored!
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*/
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uint8_t saved_pc[2];
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uint8_t saved_flg;
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/* Register save area */
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uint8_t regs[XCPTCONTEXT_SIZE];
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};
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#endif
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/* Name: up_irq_save, up_irq_restore, and friends.
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*
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* NOTE: This function should never be called from application code and,
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* as a general rule unless you really know what you are doing, this
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* function should not be called directly from operation system code either:
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* Typically, the wrapper functions, enter_critical_section() and
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* leave_critical section(), are probably what you really want.
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*/
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/* Return the current interrupt enable state and disable IRQs */
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static inline irqstate_t up_irq_save(void)
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{
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irqstate_t flags;
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__asm__ __volatile__
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(
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"\tstc flg, %0\n"
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"\tfclr I\n"
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: "=r" (flags)
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:
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: "memory");
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return flags;
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}
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/* Restore saved IRQ state */
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static inline void up_irq_restore(irqstate_t flags)
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{
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__asm__ __volatile__
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(
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"ldc %0, flg"
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:
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: "r" (flags)
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: "memory");
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}
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/* Return the current interrupt enable state and enable IRQs */
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static inline irqstate_t up_irq_enable(void)
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{
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irqstate_t flags;
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__asm__ __volatile__
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(
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"\tstc flg, %0\n"
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"\tfset I\n"
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: "=r" (flags)
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:
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: "memory");
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return flags;
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}
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#endif
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/************************************************************************************
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* Public Functions Prototypes
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************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_RENESAS_INCLUDE_M16C_IRQ_H */
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