67 lines
4.1 KiB
C
67 lines
4.1 KiB
C
/****************************************************************************
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* arch/arm/src/dm320/dm320_clkc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_DM320_DM320_CLKC_H
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#define __ARCH_ARM_SRC_DM320_DM320_CLKC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clock Controller Register Map (CLKC) *************************************/
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#define DM320_CLKC_PLLA (DM320_CLKC_REGISTER_BASE+0x0000) /* PLLA Configuration */
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#define DM320_CLKC_PLLB (DM320_CLKC_REGISTER_BASE+0x0002) /* PLLB Configuration */
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#define DM320_CLKC_SEL0 (DM320_CLKC_REGISTER_BASE+0x0004) /* Input Clock Source Selection #0 */
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#define DM320_CLKC_SEL1 (DM320_CLKC_REGISTER_BASE+0x0006) /* Input Slock Source Selection #1 */
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#define DM320_CLKC_SEL2 (DM320_CLKC_REGISTER_BASE+0x0008) /* Input Clock Source Selection #2 */
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#define DM320_CLKC_DIV0 (DM320_CLKC_REGISTER_BASE+0x000a) /* Clock Divisor Settings #0 */
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#define DM320_CLKC_DIV1 (DM320_CLKC_REGISTER_BASE+0x000c) /* Clock Divisor Settings #1 */
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#define DM320_CLKC_DIV2 (DM320_CLKC_REGISTER_BASE+0x000e) /* Clock Divisor Settings #2 */
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#define DM320_CLKC_DIV3 (DM320_CLKC_REGISTER_BASE+0x0010) /* Clock Divisor Settings #3 */
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#define DM320_CLKC_DIV4 (DM320_CLKC_REGISTER_BASE+0x0012) /* Clock Divisor Settings #4 */
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#define DM320_CLKC_BYP (DM320_CLKC_REGISTER_BASE+0x0014) /* Bypass Control */
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#define DM320_CLKC_INV (DM320_CLKC_REGISTER_BASE+0x0016) /* Inverse Control */
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#define DM320_CLKC_MOD0 (DM320_CLKC_REGISTER_BASE+0x0018) /* Module Clock Enables #0 */
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#define DM320_CLKC_MOD1 (DM320_CLKC_REGISTER_BASE+0x001a) /* Module ClockEnables #1 */
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#define DM320_CLKC_MOD2 (DM320_CLKC_REGISTER_BASE+0x001c) /* Module ClockEnables #1 */
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#define DM320_CLKC_LPCTL0 (DM320_CLKC_REGISTER_BASE+0x001e) /* Low Power Control #0 */
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#define DM320_CLKC_LPCTL1 (DM320_CLKC_REGISTER_BASE+0x0020) /* Low Power Control #1 */
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#define DM320_CLKC_OSEL (DM320_CLKC_REGISTER_BASE+0x0022) /* Output Clock Selector */
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#define DM320_CLKC_O0DIV (DM320_CLKC_REGISTER_BASE+0x0024) /* Output Clock #0 Divider */
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#define DM320_CLKC_O1DIV (DM320_CLKC_REGISTER_BASE+0x0026) /* Output Clock #1 Divider */
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#define DM320_CLKC_O2DIV (DM320_CLKC_REGISTER_BASE+0x0028) /* Output Clock #2 Divider */
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#define DM320_CLKC_PWM0C (DM320_CLKC_REGISTER_BASE+0x002a) /* PWM #0 Cycle Count */
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#define DM320_CLKC_PWM0H (DM320_CLKC_REGISTER_BASE+0x002c) /* PWM #0 High Period */
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#define DM320_CLKC_PWM1C (DM320_CLKC_REGISTER_BASE+0x002e) /* PWM #1 Cycle Count */
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#define DM320_CLKC_PWM1H (DM320_CLKC_REGISTER_BASE+0x0030) /* PWM #1 Cycle Period */
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#define DM320_CLKC_TEST0 (DM320_CLKC_REGISTER_BASE+0x08FE) /* Test #0 */
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#define DM320_CLKC_TEST1 (DM320_CLKC_REGISTER_BASE+0x08FE) /* Test #1 */
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_DM320_DM320_CLKC_H */
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