674 lines
25 KiB
Plaintext
674 lines
25 KiB
Plaintext
README
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======
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This README discusses issues unique to NuttX configurations for the
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STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6
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MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash
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memory and 300Kb SRAM. The board features:
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- On-board ST-LINK/V2 for programming and debugging,
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- Mbed-enabled (mbed.org)
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- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen
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- Camera connector
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- SAI audio codec
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- Audio line in and line out jack
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- Stereo speaker outputs
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- Two ST MEMS microphones
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- SPDIF RCA input connector
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- Two pushbuttons (user and reset)
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- 128-Mbit Quad-SPI Flash memory
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- 128-Mbit SDRAM (64 Mbits accessible)
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- Connector for microSD card
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- RF-EEPROM daughterboard connector
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- USB OTG HS with Micro-AB connectors
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- USB OTG FS with Micro-AB connectors
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- Ethernet connector compliant with IEEE-802.3-2002
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Refer to the http://www.st.com website for further information about this
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board (search keyword: stm32f746g-disco)
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Contents
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========
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- STATUS
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- Development Environment
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- LEDs and Buttons
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- Serial Console
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- Porting STM32 F4 Drivers
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- FPU
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- STM32F746G-DISCO-specific Configuration Options
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- Configurations
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STATUS
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======
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2015-07-19: The basic NSH configuration is functional using a serial
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console on USART6 and RS-232 shield. Very few other drivers are in
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place yet.
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2015-07-20: STM32 F7 Ethernet appears to be functional, but has had
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only light testing.
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2015-07-21: Added a protected build version of the NSH configuration
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(called knsh). That configuration is close: It boots, but I get
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a hard fault each time I do the NSH "help" command. Everything else
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works fine. I am thinking this is a corrupted binary; I am thinking
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that there is a bad pointer in the command table. But this is hard
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to prove but possible because the steps to produce and load the
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binary are awkward.
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Development Environment
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=======================
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The Development environments for the STM32F746G-DISCO board are identical
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to the environments for other STM32F boards. For full details on the
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environment options and setup, see the README.txt file in the
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config/stm32f746g-disco directory.
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LEDs and Buttons
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================
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LEDs
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----
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The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located
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near the reset button, that can be controlled by software (LD2 is a power
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indicator, LD3-6 indicate USB status, LD7 is controlled by the ST-Link).
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LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino
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interface. One end of LD1 is grounded so a high output on PI1 will
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illuminate the LED.
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This LED is not used by the board port unless CONFIG_ARCH_LEDS is defined.
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In that case, the usage by the board port is defined in include/board.h
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and src/stm32_leds.c. The LEDs are used to encode OS-related events as
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follows:
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SYMBOL Meaning LD1
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------------------- ----------------------- ------
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LED_STARTED NuttX has been started OFF
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LED_HEAPALLOCATE Heap has been allocated OFF
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LED_IRQSENABLED Interrupts enabled OFF
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LED_STACKCREATED Idle stack created ON
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LED_INIRQ In an interrupt N/C
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LED_SIGNAL In a signal handler N/C
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LED_ASSERTION An assertion failed N/C
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LED_PANIC The system has crashed FLASH
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Thus is LD1 is statically on, NuttX has successfully booted and is,
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apparently, running normally. If LD1 is flashing at approximately
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2Hz, then a fatal error has been detected and the system has halted.
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Buttons
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-------
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Pushbutton B1, labelled "User", is connected to GPIO PI11. A high
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value will be sensed when the button is depressed.
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Serial Console
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==============
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These configurations assume that you are using a standard Arduio RS-232
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shield with the serial interface with RX on pin D0 and TX on pin D1:
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-------- ---------------
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STM32F7
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ARDUIONO FUNCTION GPIO
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-- ----- --------- -----
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DO RX USART6_RX PC7
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D1 TX USART6_TX PC6
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-- ----- --------- -----
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Porting STM32 F4 Drivers
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========================
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The STM32F746 is very similar to the STM32 F429 and many of the drivers
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in the stm32/ directory could be ported here: ADC, BBSRAM, CAN, DAC,
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DMA2D, FLASH, I2C, IWDG, LSE, LSI, LTDC, OTGFS, OTGHS, PM, Quadrature
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Encoder, RNG, RTCC, SDMMC (was SDIO), Timer/counters, and WWDG.
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Many of these drivers would be ported very simply; many ports would just
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be a matter of copying files and some seach-and-replacement. Like:
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1. Compare the two register definitions files; make sure that the STM32
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F4 peripheral is identical (or nearly identical) to the F7
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peripheral. If so then,
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2. Copy the register definition file from the stm32/chip directory to
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the stm32f7/chip directory, making name changes as appropriate and
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updating the driver for any minor register differences.
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3. Copy the corresponding C file (and possibly a matching .h file) from
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the stm32/ directory to the stm32f7/ directory again with naming
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changes and changes for any register differences.
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4. Update the Make.defs file to include the new C file in the build.
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For other files, particularly those that use DMA, the port will be
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significantly more complex. That is because the STM32F7 has a D-Cache
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and, as a result, we need to exercise much more care to maintain cache
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coherency. There is a Wiki page discussing the issues of porting
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drivers from the stm32/ to the stm32f7/ directories here:
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http://www.nuttx.org/doku.php?id=wiki:howtos:port-drivers_stm32f7
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FPU
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===
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FPU Configuration Options
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-------------------------
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There are two version of the FPU support built into the STM32 port.
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1. Lazy Floating Point Register Save.
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This is an implementation that saves and restores FPU registers only on
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context switches. This means: (1) floating point registers are not
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stored on each context switch and, hence, possibly better interrupt
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performance. But, (2) since floating point registers are not saved,
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you cannot use floating point operations within interrupt handlers.
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This logic can be enabled by simply adding the following to your .config
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file:
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CONFIG_ARCH_FPU=y
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CONFIG_ARMV7M_CMNVECTOR=y
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CONFIG_ARMV7M_LAZYFPU=y
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2. Non-Lazy Floating Point Register Save
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Mike Smith has contributed an extensive re-write of the ARMv7-M exception
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handling logic. This includes verified support for the FPU. These changes
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have not yet been incorporated into the mainline and are still considered
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experimental. These FPU logic can be enabled with:
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CONFIG_ARCH_FPU=y
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CONFIG_ARMV7M_CMNVECTOR=y
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You will probably also changes to the ld.script in if this option is selected.
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This should work:
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-ENTRY(_stext)
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+ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
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+EXTERN(_vectors) /* Force the vectors to be included in the output */
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STM32F746G-DISCO-specific Configuration Options
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===============================================
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CONFIG_ARCH - Identifies the arch/ subdirectory. This should
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be set to:
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CONFIG_ARCH=arm
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CONFIG_ARCH_family - For use in C code:
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CONFIG_ARCH_ARM=y
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CONFIG_ARCH_architecture - For use in C code:
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CONFIG_ARCH_CORTEXM7=y
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CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
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CONFIG_ARCH_CHIP=stm32f7
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CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
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chip:
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CONFIG_ARCH_CHIP_STM32F746=y
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
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configuration features.
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
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CONFIG_ARCH_BOARD - Identifies the configs/ subdirectory and,
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hence, the board that supports the particular chip or SoC.
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CONFIG_ARCH_BOARD=stm32f746g-disco (for the STM32F746G-DISCO development board)
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CONFIG_ARCH_BOARD_name - For use in C code
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CONFIG_ARCH_BOARD_STM32F746G_DISCO=y
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CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
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of delay loops
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CONFIG_ENDIAN_BIG - should not be defined.
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CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
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CONFIG_RAM_SIZE=0x00010000 (64Kb)
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CONFIG_RAM_START - The start address of installed SRAM (SRAM1)
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CONFIG_RAM_START=0x20010000
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CONFIG_RAM_SIZE=245760
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This configurations use only SRAM1 for data storage. The heap includes
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the remainder of SRAM1. If CONFIG_MM_REGIONS=2, then SRAM2 will be
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included in the heap.
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DTCM SRAM is never included in the heap because it cannot be used for
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DMA. A DTCM allocator is available, however, so that DTCM can be
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managed with dtcm_malloc(), dtcm_free(), etc.
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In order to use FSMC SRAM, the following additional things need to be
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present in the NuttX configuration file:
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CONFIG_STM32F7_FSMC_SRAM - Indicates that SRAM is available via the
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FSMC (as opposed to an LCD or FLASH).
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CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
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CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)
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CONFIG_ARCH_FPU - The STM32F746G-DISCO supports a floating point unit (FPU)
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CONFIG_ARCH_FPU=y
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
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have LEDs
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CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
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CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
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cause a 100 second delay during boot-up. This 100 second delay
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serves no purpose other than it allows you to calibrate
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CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
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the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
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the delay actually is 100 seconds.
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Individual subsystems can be enabled:
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APB1
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----
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CONFIG_STM32F7_TIM2 TIM2
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CONFIG_STM32F7_TIM3 TIM3
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CONFIG_STM32F7_TIM4 TIM4
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CONFIG_STM32F7_TIM5 TIM5
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CONFIG_STM32F7_TIM6 TIM6
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CONFIG_STM32F7_TIM7 TIM7
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CONFIG_STM32F7_TIM12 TIM12
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CONFIG_STM32F7_TIM13 TIM13
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CONFIG_STM32F7_TIM14 TIM14
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CONFIG_STM32F7_LPTIM1 LPTIM1
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CONFIG_STM32F7_RTC RTC
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CONFIG_STM32F7_BKP BKP Registers
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CONFIG_STM32F7_WWDG WWDG
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CONFIG_STM32F7_IWDG IWDG
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CONFIG_STM32F7_SPI2 SPI2
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CONFIG_STM32F7_I2S2 I2S2
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CONFIG_STM32F7_SPI3 SPI3
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CONFIG_STM32F7_I2S3 I2S3
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CONFIG_STM32F7_SPDIFRX SPDIFRX
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CONFIG_STM32F7_USART2 USART2
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CONFIG_STM32F7_USART3 USART3
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CONFIG_STM32F7_UART4 UART4
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CONFIG_STM32F7_UART5 UART5
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CONFIG_STM32F7_I2C1 I2C1
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CONFIG_STM32F7_I2C2 I2C2
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CONFIG_STM32F7_I2C3 I2C3
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CONFIG_STM32F7_I2C4 I2C4
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CONFIG_STM32F7_CAN1 CAN1
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CONFIG_STM32F7_CAN2 CAN2
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CONFIG_STM32F7_HDMICEC HDMI-CEC
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CONFIG_STM32F7_PWR PWR
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CONFIG_STM32F7_DAC DAC
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CONFIG_STM32F7_UART7 UART7
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CONFIG_STM32F7_UART8 UART8
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APB2
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----
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CONFIG_STM32F7_TIM1 TIM1
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CONFIG_STM32F7_TIM8 TIM8
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CONFIG_STM32F7_USART1 USART1
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CONFIG_STM32F7_USART6 USART6
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CONFIG_STM32F7_ADC ADC1 - ADC2 - ADC3
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CONFIG_STM32F7_SDMMC1 SDMMC1
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CONFIG_STM32F7_SPI1 SPI1
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CONFIG_STM32F7_SPI4 SPI4
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CONFIG_STM32F7_SYSCFG SYSCFG
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CONFIG_STM32F7_EXTI EXTI
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CONFIG_STM32F7_TIM9 TIM9
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CONFIG_STM32F7_TIM10 TIM10
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CONFIG_STM32F7_TIM11 TIM11
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CONFIG_STM32F7_SPI5 SPI5
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CONFIG_STM32F7_SPI6 SPI6
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CONFIG_STM32F7_SAI1 SAI1
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CONFIG_STM32F7_SAI2 SAI2
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CONFIG_STM32F7_LTDC LCD-TFT
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AHB1
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----
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CONFIG_STM32F7_CRC CRC
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CONFIG_STM32F7_BKPSRAM BKPSRAM
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CONFIG_STM32F7_DMA1 DMA1
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CONFIG_STM32F7_DMA2 DMA2
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CONFIG_STM32F7_ETHMAC Ethernet MAC
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CONFIG_STM32F7_DMA2D Chrom-ART (DMA2D)
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CONFIG_STM32F7_USBOTGHS USB OTG HS
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AHB2
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----
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CONFIG_STM32F7_USBOTGFS USB OTG FS
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CONFIG_STM32F7_DCMI DCMI
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CONFIG_STM32F7_CRYP CRYP
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CONFIG_STM32F7_HASH HASH
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CONFIG_STM32F7_RNG RNG
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AHB3
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----
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CONFIG_STM32F7_FSMC FSMC control registers
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CONFIG_STM32F7_QUADSPI QuadSPI Control
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Timer devices may be used for different purposes. One special purpose is
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to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn
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is defined (as above) then the following may also be defined to indicate that
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the timer is intended to be used for pulsed output modulation, ADC conversion,
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or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
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to assign the timer (n) for used by the ADC or DAC, but then you also have to
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configure which ADC or DAC (m) it is assigned to.
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CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
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CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
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CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
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CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
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CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
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For each timer that is enabled for PWM usage, we need the following additional
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configuration settings:
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CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
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NOTE: The STM32 timers are each capable of generating different signals on
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each of the four channels with different duty cycles. That capability is
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not supported by this driver: Only one output channel per timer.
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STM32F746G-DISCO specific device driver settings
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CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
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m (m=4,5) for the console and ttys0 (default is the USART1).
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CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
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This specific the size of the receive buffer
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CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
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being sent. This specific the size of the transmit buffer
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CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
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CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
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CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
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CONFIG_U[S]ARTn_2STOP - Two stop bits
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STM32F746G-DISCO CAN Configuration
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CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32F7_CAN1 or
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CONFIG_STM32F7_CAN2 must also be defined)
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CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
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Standard 11-bit IDs.
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CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
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Default: 8
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CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
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Default: 4
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CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
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mode for testing. The STM32 CAN driver does support loopback mode.
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CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN1 is defined.
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CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined.
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CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
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CONFIG_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
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CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
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dump of all CAN registers.
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STM32F746G-DISCO SPI Configuration
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CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI
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support. Non-interrupt-driven, poll-waiting is recommended if the
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interrupt rate would be to high in the interrupt driven case.
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CONFIG_STM32F7_SPI_DMA - Use DMA to improve SPI transfer performance.
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Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT.
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STM32F746G-DISCO DMA Configuration
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CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32F7_SDIO
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and CONFIG_STM32F7_DMA2.
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CONFIG_SDIO_PRI - Select SDIO interrupt prority. Default: 128
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CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
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Default: Medium
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CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
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4-bit transfer mode.
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STM32 USB OTG FS Host Driver Support
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Pre-requisites
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CONFIG_USBDEV - Enable USB device support
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CONFIG_USBHOST - Enable USB host support
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CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
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CONFIG_STM32F7_SYSCFG - Needed
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CONFIG_SCHED_WORKQUEUE - Worker thread support is required
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Options:
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CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
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Default 128 (512 bytes)
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CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
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in 32-bit words. Default 96 (384 bytes)
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CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
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words. Default 96 (384 bytes)
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CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
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CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
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want to do that?
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CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access
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debug. Depends on CONFIG_DEBUG_FEATURES.
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CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
|
packets. Depends on CONFIG_DEBUG_FEATURES.
|
|
|
|
Configurations
|
|
==============
|
|
|
|
Common Configuration Information
|
|
--------------------------------
|
|
Each STM32F746G-DISCO configuration is maintained in a sub-directory and
|
|
can be selected as follow:
|
|
|
|
cd tools
|
|
./configure.sh stm32f746g-disco/<subdir>
|
|
cd -
|
|
. ./setenv.sh
|
|
|
|
If this is a Windows native build, then configure.bat should be used
|
|
instead of configure.sh:
|
|
|
|
configure.bat STM32F746G-DISCO\<subdir>
|
|
|
|
Where <subdir> is one of the sub-directories listed below.
|
|
|
|
NOTES:
|
|
|
|
1. These configurations use the mconf-based configuration tool. To
|
|
change this configuration using that tool, you should:
|
|
|
|
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
|
see additional README.txt files in the NuttX tools repository.
|
|
|
|
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
|
reconfiguration process.
|
|
|
|
2. By default, these configurations use the USART6 for the serial
|
|
console. Pins are configured to that RX/TX are available at
|
|
pins D0 and D1 of the Arduion connectors. This should be compatible
|
|
with most RS-232 shields.
|
|
|
|
3. All of these configurations are set up to build under Windows using the
|
|
"GNU Tools for ARM Embedded Processors" that is maintained by ARM
|
|
(unless stated otherwise in the description of the configuration).
|
|
|
|
https://launchpad.net/gcc-arm-embedded
|
|
|
|
As of this writing (2015-03-11), full support is difficult to find
|
|
for the Cortex-M7, but is supported by at least this realeasse of
|
|
the ARM GNU tools:
|
|
|
|
https://launchpadlibrarian.net/192228215/release.txt
|
|
|
|
Current (2105-07-31) setenv.sh file are configured to use this
|
|
release:
|
|
|
|
https://launchpadlibrarian.net/209776344/release.txt
|
|
|
|
That toolchain selection can easily be reconfigured using
|
|
'make menuconfig'. Here are the relevant current settings:
|
|
|
|
Build Setup:
|
|
CONFIG_HOST_WINDOWS=y : Window environment
|
|
CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows
|
|
|
|
System Type -> Toolchain:
|
|
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain
|
|
|
|
NOTE: As of this writing, there are issues with using this tool at
|
|
the -Os level of optimization. This has not been proven to be a
|
|
compiler issue (as least not one that might not be fixed with a
|
|
well placed volatile qualifier). However, in any event, it is
|
|
recommend that you use not more that -O2 optimization.
|
|
|
|
Configuration Directories
|
|
-------------------------
|
|
|
|
kostest:
|
|
-------
|
|
This is identical to the nsh configuration below except that NuttX is
|
|
built as a kernel-mode, monolithic module and the user applications are
|
|
built separately. Is is recommended to use a special make command;
|
|
not just 'make' but make with the following two arguments:
|
|
|
|
make pass1 pass2
|
|
|
|
In the normal case (just 'make'), make will attempt to build both user-
|
|
and kernel-mode blobs more or less interleaved. This actual works!
|
|
However, for me it is very confusing so I prefer the above make command:
|
|
Make the user-space binaries first (pass1), then make the kernel-space
|
|
binaries (pass2)
|
|
|
|
NOTES:
|
|
|
|
1. At the end of the build, there will be several files in the top-level
|
|
NuttX build directory:
|
|
|
|
PASS1:
|
|
nuttx_user.elf - The pass1 user-space ELF file
|
|
nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig)
|
|
User.map - Symbols in the user-space ELF file
|
|
|
|
PASS2:
|
|
nuttx - The pass2 kernel-space ELF file
|
|
nuttx.hex - The pass2 Intel HEX file (selected in defconfig)
|
|
System.map - Symbols in the kernel-space ELF file
|
|
|
|
2. Combining .hex files. If you plan to use the STM32 ST-Link Utility to
|
|
load the .hex files into FLASH, then you need to combine the two hex
|
|
files into a single .hex file. Here is how you can do that.
|
|
|
|
a. The 'tail' of the nuttx.hex file should look something like this
|
|
(with my comments added):
|
|
|
|
$ tail nuttx.hex
|
|
# 00, data records
|
|
...
|
|
:10 9DC0 00 01000000000800006400020100001F0004
|
|
:10 9DD0 00 3B005A0078009700B500D400F300110151
|
|
:08 9DE0 00 30014E016D0100008D
|
|
# 05, Start Linear Address Record
|
|
:04 0000 05 0800 0419 D2
|
|
# 01, End Of File record
|
|
:00 0000 01 FF
|
|
|
|
Use an editor such as vi to remove the 05 and 01 records.
|
|
|
|
b. The 'head' of the nuttx_user.hex file should look something like
|
|
this (again with my comments added):
|
|
|
|
$ head nuttx_user.hex
|
|
# 04, Extended Linear Address Record
|
|
:02 0000 04 0801 F1
|
|
# 00, data records
|
|
:10 8000 00 BD89 01084C800108C8110208D01102087E
|
|
:10 8010 00 0010 00201C1000201C1000203C16002026
|
|
:10 8020 00 4D80 01085D80010869800108ED83010829
|
|
...
|
|
|
|
Nothing needs to be done here. The nuttx_user.hex file should
|
|
be fine.
|
|
|
|
c. Combine the edited nuttx.hex and un-edited nuttx_user.hex
|
|
file to produce a single combined hex file:
|
|
|
|
$ cat nuttx.hex nuttx_user.hex >combined.hex
|
|
|
|
Then use the combined.hex file with the STM32 ST-Link tool. The
|
|
mbed interface does not seem to except .hex files, but you can
|
|
also convert the .hex file to binary with this command:
|
|
|
|
arm-none-eabi-objcopy.exe -I ihex -O binary combined.hex combined.bin
|
|
|
|
If you do this a lot, you will probably want to invest a little time
|
|
to develop a tool to automate these steps.
|
|
|
|
netnsh:
|
|
------
|
|
This is a NetShell (NSH) very similar to the nsh configuration described
|
|
below. It differs in that it has networking enabled.
|
|
|
|
NOTES:
|
|
|
|
1. Both IPv4 and IPv6 protocoals are enabled. Fixed IP addresses are
|
|
used. The default configurationi target has these IP address:
|
|
|
|
IPv4: 10.0.0.2
|
|
IPv6: fc00::2
|
|
|
|
These are, of course, easily changes by reconfiguring via 'make
|
|
menuconfig'
|
|
|
|
2. UDP, TCIP/IP, ARP, ICMP, and ICMPv6 are also enabled.
|
|
|
|
3. NSH offers several network oriented commands such as: ipconfig,
|
|
ifup, ifdown, ping, and ping6.
|
|
|
|
4. Telnet sessions are supported. You can start a Telnet session from
|
|
any host on the network using a command like:
|
|
|
|
$ telnet 10.0.0.2
|
|
Trying 10.0.0.2...
|
|
Connected to 10.0.0.2.
|
|
Escape character is '^]'.
|
|
|
|
NuttShell (NSH) NuttX-7.10
|
|
nsh> help
|
|
help usage: help [-v] [<cmd>]
|
|
|
|
[ dd hexdump mb ping6 sleep
|
|
? echo ifconfig mkdir ps test
|
|
break exec ifdown mkfifo pwd true
|
|
cat exit ifup mh rm uname
|
|
cd false kill mv rmdir unset
|
|
cp free losetup mw set usleep
|
|
cmp help ls ping sh xd
|
|
|
|
Builtin Apps:
|
|
nsh>
|
|
|
|
Under either Linux or Cygwin
|
|
|
|
5. The PHY address is either 0 or 1, depending on the state of the
|
|
LAN8720 RXER/PHYAD0 when the hardware is reset. That connects to the
|
|
STM32 F7 via PG2. PG2 is not controlled but appears to result in a
|
|
PHY address of 0.
|
|
|
|
nsh:
|
|
---
|
|
Configures the NuttShell (NSH) located at apps/examples/nsh. The
|
|
Configuration enables the serial interfaces on UART6. Support for
|
|
builtin applications is enabled, but in the base configuration no
|
|
builtin applications are selected.
|