162 lines
8.0 KiB
C
162 lines
8.0 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-a/scu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Reference:
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* Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
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* 0407I (ID091612).
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*/
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#ifndef __ARCH_ARM_SRC_ARMV7_A_SCU_H
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#define __ARCH_ARM_SRC_ARMV7_A_SCU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "mpcore.h" /* For MPCORE_SCU_VBASE */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define SCU_CTRL_OFFSET 0x0000 /* SCU Control Register (Implementation defined) */
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#define SCU_CONFIG_OFFSET 0x0004 /* SCU Configuration Register (Implementation defined) */
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#define SCU_PWRSTATUS_OFFSET 0x0008 /* SCU CPU Power Status Register */
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#define SCU_INVALIDATE_OFFSET 0x000c /* SCU Invalidate All Registers in Secure State */
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#define SCU_FILTERSTART_OFFSET 0x0040 /* Filtering Start Address Register Defined by FILTERSTART input */
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#define SCU_FILTEREND_OFFSET 0x0044 /* Filtering End Address Register Defined by FILTEREND input */
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#define SCU_SAC_OFFSET 0x0050 /* SCU Access Control (SAC) Register */
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#define SCU_SNSAC_OFFSET 0x0054 /* SCU Non-secure Access Control (SNSAC) Register */
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/* Register addresses *******************************************************/
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#define SCU_CTRL (MPCORE_SCU_VBASE+SCU_CTRL_OFFSET)
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#define SCU_CONFIG (MPCORE_SCU_VBASE+SCU_CONFIG_OFFSET)
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#define SCU_PWRSTATUS (MPCORE_SCU_VBASE+SCU_PWRSTATUS_OFFSET)
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#define SCU_INVALIDATE (MPCORE_SCU_VBASE+SCU_INVALIDATE_OFFSET)
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#define SCU_FILTERSTART (MPCORE_SCU_VBASE+SCU_FILTERSTART_OFFSET)
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#define SCU_FILTEREND (MPCORE_SCU_VBASE+SCU_FILTEREND_OFFSET)
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#define SCU_SAC (MPCORE_SCU_VBASE+SCU_SAC_OFFSET)
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#define SCU_SNSAC (MPCORE_SCU_VBASE+SCU_SNSAC_OFFSET)
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/* Register bit-field definitions *******************************************/
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/* SCU Control Register (Implementation defined) */
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#define SCU_CTRL_ENABLE (1 << 0) /* SCU enable */
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#define SCU_CTRL_ADDRFILTER (1 << 1) /* Address filtering enable */
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#define SCU_CTRL_RAMPARITY (1 << 2) /* SCU RAMs parity enable */
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#define SCU_CTRL_LINFILL (1 << 3) /* SCU speculative linefill enable */
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#define SCU_CTRL_PORT0 (1 << 4) /* Force all device to port0 enable */
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#define SCU_CTRL_STANDBY (1 << 5) /* SCU standby enable */
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#define SCU_CTRL_ICSTANDBY (1 << 6) /* IC standby enable */
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/* SCU Configuration Register (Implementation defined) */
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#define SCU_CONFIG_NCPUS_SHIFT 0 /* CPU number Number of CPUs present */
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#define SCU_CONFIG_NCPUS_MASK (3 << SCU_CONFIG_NCPUS_SHIFT)
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# define SCU_CONFIG_NCPUS(r) ((((uint32_t)(r) & SCU_CONFIG_NCPUS_MASK) >> SCU_CONFIG_NCPUS_SHIFT) + 1)
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#define SCU_CONFIG_SMPCPUS_SHIFT 4 /* Processors that are in SMP or AMP mode */
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#define SCU_CONFIG_SMPCPUS_MASK (15 << SCU_CONFIG_SMPCPUS_SHIFT)
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# define SCU_CONFIG_CPU_SMP(n) (1 << ((n)+4))
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# define SCU_CONFIG_CPU0_SMP (1 << 4)
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# define SCU_CONFIG_CPU1_SMP (1 << 5)
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# define SCU_CONFIG_CPU2_SMP (1 << 6)
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# define SCU_CONFIG_CPU3_SMP (1 << 7)
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#define SCU_CONFIG_TAGRAM_16KB 0
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#define SCU_CONFIG_TAGRAM_32KB 1
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#define SCU_CONFIG_TAGRAM_64KB 2
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#define SCU_CONFIG_CPU0_TAGRAM_SHIFT 8 /* CPU 0 tag RAM size */
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#define SCU_CONFIG_CPU0_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
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#define SCU_CONFIG_CPU1_TAGRAM_SHIFT 10 /* CPU 1 tag RAM size */
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#define SCU_CONFIG_CPU1_TAGRAM_MASK (3 << SCU_CONFIG_CPU1_TAGRAM_SHIFT)
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#define SCU_CONFIG_CPU2_TAGRAM_SHIFT 12 /* CPU 2 tag RAM size */
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#define SCU_CONFIG_CPU2_TAGRAM_MASK (3 << SCU_CONFIG_CPU2_TAGRAM_SHIFT)
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#define SCU_CONFIG_CPU3_TAGRAM_SHIFT 14 /* CPU 3 tag RAM size */
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#define SCU_CONFIG_CPU3_TAGRAM_MASK (3 << SCU_CONFIG_CPU3_TAGRAM_SHIFT)
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/* SCU CPU Power Status Register */
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#define SCU_PWRSTATUS_NORMAL 0
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#define SCU_PWRSTATUS_DORMANT 2
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#define SCU_PWRSTATUS_PWROFF 3
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#define SCU_PWRSTATUS_CPU0_SHIFT 0 /* CPU0 status Power status */
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#define SCU_PWRSTATUS_CPU0_MASK (3 << SCU_PWRSTATUS_CPU0_SHIFT)
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#define SCU_PWRSTATUS_CPU1_SHIFT 8 /* CPU1 status Power status */
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#define SCU_PWRSTATUS_CPU1_MASK (3 << SCU_PWRSTATUS_CPU1_SHIFT)
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#define SCU_PWRSTATUS_CPU2_SHIFT 16 /* CPU2 status Power status */
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#define SCU_PWRSTATUS_CPU2_MASK (3 << SCU_PWRSTATUS_CPU2_SHIFT)
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#define SCU_PWRSTATUS_CPU3_SHIFT 24 /* CPU3 status Power status */
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#define SCU_PWRSTATUS_CPU3_MASK (3 << SCU_PWRSTATUS_CPU3_SHIFT)
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/* SCU Invalidate All Registers in Secure State */
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#define SCU_INVALIDATE_ALL_WAYS 15
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#define SCU_INVALIDATE_CPU0_SHIFT 0 /* Ways that must be invalidated for CPU0 */
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#define SCU_INVALIDATE_CPU0_MASK (15 << SCU_INVALIDATE_CPU0_SHIFT)
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#define SCU_INVALIDATE_CPU1_SHIFT 4 /* Ways that must be invalidated for CPU1 */
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#define SCU_INVALIDATE_CPU1_MASK (15 << SCU_INVALIDATE_CPU1_SHIFT)
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#define SCU_INVALIDATE_CPU2_SHIFT 8 /* Ways that must be invalidated for CPU2 */
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#define SCU_INVALIDATE_CPU2_MASK (15 << SCU_INVALIDATE_CPU2_SHIFT)
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#define SCU_INVALIDATE_CPU3_SHIFT 12 /* Ways that must be invalidated for CPU3 */
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#define SCU_INVALIDATE_CPU3_MASK (15 << SCU_INVALIDATE_CPU3_SHIFT)
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/* Filtering Start Address Register Defined by FILTERSTART input */
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#define SCU_FILTERSTART_SHIFT 10 /* Filtering start address */
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#define SCU_FILTERSTART_MASK (0xfff << SCU_FILTERSTART_SHIFT)
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/* Filtering End Address Register Defined by FILTEREND input */
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#define SCU_FILTEREND_SHIFT 10 /* Filtering start address */
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#define SCU_FILTEREND_MASK (0xfff << SCU_FILTEREND_SHIFT)
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/* SCU Access Control (SAC) Register */
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#define SCU_SAC_CPU(n) (1 << (n)) /* CPUn may access components */
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/* SCU Non-secure Access Control (SNSAC) Register */
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#define SCU_SNSAC_COMP_CPU(n) (1 << (n)) /* CPUn has non-secure access to components */
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#define SCU_SNSAC_PTIM_CPU(n) (1 << ((n)+4)) /* CPUn has non-secure access to private timers */
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#define SCU_SNSAC_GTIM_CPU(n) (1 << ((n)+8)) /* CPUn has non-secure access to global timer */
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: arm_enable_smp
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*
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* Description:
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* Enable the SCU and make certain that current CPU is participating in
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* the SMP cache coherency.
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*
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****************************************************************************/
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void arm_enable_smp(int cpu);
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#endif /* __ARCH_ARM_SRC_ARMV7_A_SCU_H */
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