40cd67eee6
Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
133 lines
4.6 KiB
C
133 lines
4.6 KiB
C
/****************************************************************************
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* boards/arm/dm320/ntosd-dm320/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_DM320_NTOSD_DM320_INCLUDE_BOARD_H
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#define __BOARDS_ARM_DM320_NTOSD_DM320_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* This platform has the ARM at 175 MHz and the DSP at 101.25 MHz */
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#define DM320_ARM_CLOCK 175500000
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#define DM320_SDR_CLOCK 101250000
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#define DM320_DSP_CLOCK 101250000
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#define DM320_AXL_CLOCK 175500000
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#define DM320_AHB_CLOCK 87750000
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/* UART0/1 and TIMER0/1 are clocked by PLLIN=27MHz */
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#define CONFIG_DM320_UARTPPLIN 1
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/* Configuration for dm9000 network device */
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#define DM9000_BASE CONFIG_DM9000_BASE
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/* Memory Map ***************************************************************/
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/* The Neuros development board has 16MiB RAM starting at 0x01000000
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* (physical) and 8MiB of FLASH.
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* The Neuros OSD 1.0 consumer has 32MiB RAM starting at 0x01100000
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* (physical) and 16MiB of FLASH.
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*
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* FIXME: Flash location may also differ on OSD 1.0 consumer unit!
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*/
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#ifdef CONFIG_ARCH_NTOSD_DEVBOARD
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# if CONFIG_RAM_START != 0x01000000
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# error "Invalid setting for CONFIG_RAM_START"
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# endif
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# if CONFIG_RAM_SIZE != 0x01000000
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# warning "Check CONFIG_RAM_SIZE. This Neuros OSD has 0x01000000 bytes of SDRAM"
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# endif
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# define DM320_SDRAM_PSECTION 0x01000000 /* 496Mb many section -- */
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# define DM320_SDRAM_PADDR 0x01000000 /* 496Mb many sections CW */
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#else
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# if CONFIG_RAM_START != 0x01100000
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# error "Invalid setting for CONFIG_RAM_START"
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# endif
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# if CONFIG_RAM_SIZE != 0x02000000
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# warning "Check CONFIG_RAM_SIZE. This Neuros OSD has 0x02000000 bytes of SDRAM"
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# endif
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# define DM320_SDRAM_PSECTION 0x01100000 /* 496Mb many section -- */
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# define DM320_SDRAM_PADDR 0x01100000 /* 496Mb many sections CW */
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#endif
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/* GIO keyboard (GIO 1-5) */
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#define KEY_MASK 0x003E
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#define KEY_SCAN0_BIT 0x0002
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#define KEY_SCAN1_BIT 0x0004
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#define KEY_SCAN2_BIT 0x0008
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#define KEY_SCAN3_BIT 0x0010
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#define KEY_SCAN4_BIT 0x0020
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#define KEY_GIO_DIR0_VAL KEY_MASK /* Configure as INPUT */
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#define KEY_GIO_INV0_VAL KEY_MASK /* All inverted */
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#define KEY_GIO_SET0_VAL (0) /* Initialized to zero */
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#define KEY_GIO_CLR0_VAL (0)
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#define GIO_KEY_SCAN0 1
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#define GIO_KEY_SCAN1 2
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#define GIO_KEY_SCAN2 3
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#define GIO_KEY_SCAN3 4
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#define GIO_KEY_SCAN4 5
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#define GIO_MS_DETECT 5
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#define GIO_DM9000A_INT 6
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#define GIO_MMC_DETECT 8
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#define GIO_CFC_DETECT 9
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#define GIO_VIDEO_IN 10
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#define GIO_LED_RED 16
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#define GIO_LED_GREEN 17
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#define GIO_CFC_ENABLE 25
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#define GIO_I2C_SCL 30
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#define GIO_I2C_SDA 31
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#define GIO_ENA_VIDEO 32
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#define GIO_CFC_RESET 36
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#define GIO_CFC_STSCHG 37
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/* LED Usage */
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED GIO_LED_GREEN
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#define LED_INIRQ GIO_LED_RED
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#define LED_SIGNAL GIO_LED_RED
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#define LED_ASSERTION GIO_LED_RED
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#define LED_PANIC GIO_LED_RED
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#define LED_IDLE 0
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#endif
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#endif /* __BOARDS_ARM_DM320_NTOSD_DM320_INCLUDE_BOARD_H */
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