228 lines
7.7 KiB
C
228 lines
7.7 KiB
C
/****************************************************************************
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* boards/arm/stm32/stm32f103-minimum/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* On-board crystal frequency is 8MHz (HSE) */
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#define STM32_BOARD_XTAL 8000000ul
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/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is
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* 8MHz (XTAL) x 9 = 72MHz
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*/
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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/* APB2 timers 1 and 8 will receive PCLK2. */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-7 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* USB divider -- Divide PLL clock by 1.5 */
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#define STM32_CFGR_USBPRE 0
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
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*/
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* BUTTON definitions *******************************************************/
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#define NUM_BUTTONS 2
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#define BUTTON_USER1 0
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#define BUTTON_USER2 1
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#define BUTTON_USER1_BIT (1 << BUTTON_USER1)
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#define BUTTON_USER2_BIT (1 << BUTTON_USER2)
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/* LED definitions **********************************************************/
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/* Define how many LEDs this board has (needed by userleds) */
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#define BOARD_NLEDS 1
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/* The board has only one controllable LED */
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#define LED_STARTED 0 /* No LEDs */
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#define LED_HEAPALLOCATE 1 /* LED1 on */
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#define LED_IRQSENABLED 2 /* LED2 on */
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#define LED_STACKCREATED 3 /* LED1 on */
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#define LED_INIRQ 4 /* LED1 off */
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#define LED_SIGNAL 5 /* LED2 on */
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#define LED_ASSERTION 6 /* LED1 + LED2 */
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#define LED_PANIC 7 /* LED1 / LED2 blinking */
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/* PWM
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*
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* The STM32F103-Minimum has no real on-board PWM devices, but the board can
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* be configured to output a pulse train using TIM3 CH3 on PB0.
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*
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* Note: we don't need redefine GPIO_TIM3_CH3OUT because PB0 is not
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* remap pin.
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*/
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/* RGB LED
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*
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* R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9
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*
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* Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT
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*/
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#define RGBLED_RPWMTIMER 1
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#define RGBLED_RPWMCHANNEL 1
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#define RGBLED_GPWMTIMER 2
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#define RGBLED_GPWMCHANNEL 2
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#define RGBLED_BPWMTIMER 4
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#define RGBLED_BPWMCHANNEL 4
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/* Tone Driver **************************************************************/
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#define BOARD_TONE_PWM_TIM 2 /* PWM timer for tone generation */
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#define BOARD_TONE_ONESHOT_TIM 3 /* Oneshot timer for note timings */
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#define BOARD_TONE_ONESHOT_TIM_RES 10 /* Oneshot timer resolution (us) */
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/* NRF24L01 Driver **********************************************************/
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/* Chip enable: PB.1 */
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#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1)
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/* IRQ line: PA.0 */
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#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0)
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#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE
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#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ
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/* HCSR04 driver */
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/* Pins config to use with HC-SR04 sensor */
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#define GPIO_HCSR04_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_HCSR04_TRIG (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1)
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#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT
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#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG
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#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */
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/* Pin for APDS-9960 sensor */
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#define GPIO_APDS9960_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0)
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#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT
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/* ZERO CROSS pin definition */
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#define BOARD_ZEROCROSS_GPIO \
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(GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0)
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#endif /* __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H */
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