291 lines
17 KiB
C
291 lines
17 KiB
C
/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_spi.h
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* Serial Peripheral Interface (SPI) definitions for the SAM3U, SAM4S, SAM4E, and SAM4L
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*
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* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* General definitions ******************************************************************/
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#define SAM_SPI_NCS 4 /* Four chip selects */
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/* SPI register offsets *****************************************************************/
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#define SAM_SPI_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_SPI_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_SPI_RDR_OFFSET 0x0008 /* Receive Data Register */
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#define SAM_SPI_TDR_OFFSET 0x000c /* Transmit Data Register */
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#define SAM_SPI_SR_OFFSET 0x0010 /* Status Register */
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#define SAM_SPI_IER_OFFSET 0x0014 /* Interrupt Enable Register */
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#define SAM_SPI_IDR_OFFSET 0x0018 /* Interrupt Disable Register */
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#define SAM_SPI_IMR_OFFSET 0x001c /* Interrupt Mask Register */
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/* 0x20-0x2c: Reserved */
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#define SAM_SPI_CSR0_OFFSET 0x0030 /* Chip Select Register 0 */
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#define SAM_SPI_CSR1_OFFSET 0x0034 /* Chip Select Register 1 */
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#define SAM_SPI_CSR2_OFFSET 0x0038 /* Chip Select Register 2 */
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#define SAM_SPI_CSR3_OFFSET 0x003c /* Chip Select Register 3 */
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/* 0x40-0xe0: Reserved */
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#define SAM_SPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
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#define SAM_SPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
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/* 0xec-0xf4: Reserved */
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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# define SAM_SPI_FEATURES_OFFSET 0x00f8 /* Features Register */
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# define SAM_SPI_VERSION_OFFSET 0x00fc /* Version Register */
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#endif
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/* 0x100-0x124 Reserved for PDC Registers */
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/* SPI register addresses ***************************************************************/
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#define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */
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#define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */
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#define SAM_SPI0_RDR (SAM_SPI0_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */
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#define SAM_SPI0_TDR (SAM_SPI0_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */
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#define SAM_SPI0_SR (SAM_SPI0_BASE+SAM_SPI_SR_OFFSET) /* Status Register */
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#define SAM_SPI0_IER (SAM_SPI0_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */
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#define SAM_SPI0_IDR (SAM_SPI0_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */
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#define SAM_SPI0_IMR (SAM_SPI0_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */
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#define SAM_SPI0_CSR0 (SAM_SPI0_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
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#define SAM_SPI0_CSR1 (SAM_SPI0_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
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#define SAM_SPI0_CSR2 (SAM_SPI0_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
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#define SAM_SPI0_CSR3 (SAM_SPI0_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
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#define SAM_SPI0_WPCR (SAM_SPI0_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
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#define SAM_SPI0_WPSR (SAM_SPI0_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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# define SAM_SPI0_FEATURES (SAM_SPI0_BASE+SAM_SPI_FEATURES_OFFSET)
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# define SAM_SPI0_VERSION (SAM_SPI0_BASE+SAM_SPI_VERSION_OFFSET)
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#endif
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#define SAM_SPI1_CR (SAM_SPI1_BASE+SAM_SPI_CR_OFFSET) /* Control Register */
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#define SAM_SPI1_MR (SAM_SPI1_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */
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#define SAM_SPI1_RDR (SAM_SPI1_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */
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#define SAM_SPI1_TDR (SAM_SPI1_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */
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#define SAM_SPI1_SR (SAM_SPI1_BASE+SAM_SPI_SR_OFFSET) /* Status Register */
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#define SAM_SPI1_IER (SAM_SPI1_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */
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#define SAM_SPI1_IDR (SAM_SPI1_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */
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#define SAM_SPI1_IMR (SAM_SPI1_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */
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#define SAM_SPI1_CSR0 (SAM_SPI1_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
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#define SAM_SPI1_CSR1 (SAM_SPI1_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
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#define SAM_SPI1_CSR2 (SAM_SPI1_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
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#define SAM_SPI1_CSR3 (SAM_SPI1_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
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#define SAM_SPI1_WPCR (SAM_SPI1_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
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#define SAM_SPI1_WPSR (SAM_SPI1_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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# define SAM_SPI1_FEATURES (SAM_SPI1_BASE+SAM_SPI_FEATURES_OFFSET)
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# define SAM_SPI1_VERSION (SAM_SPI1_BASE+SAM_SPI_VERSION_OFFSET)
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#endif
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/* SPI register bit definitions *********************************************************/
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/* SPI Control Register */
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#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */
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#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */
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#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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# define SPI_CR_FLUSHFIFO (1 << 8) /* Bit 8: Flush Fifo Command */
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#endif
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#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* SPI Mode Register */
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#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
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#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
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#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
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#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
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#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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# define SPI_MR_RXFIFOEN (1 << 6) /* Bit 6: FIFO in Reception Enable */
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#endif
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#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */
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#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT)
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# define SPI_MR_PCS0 (0 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
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# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
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# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
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# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
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#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
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#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT)
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/* SPI Receive Data Register */
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#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
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#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT)
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#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT)
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# define SPI_RDR_PCS0 (0 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
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# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
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# define SPI_RDR_PCS2 (3 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
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# define SPI_RDR_PCS3 (7 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
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/* SPI Transmit Data Register */
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#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
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#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT)
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#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT)
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# define SPI_TDR_PCS0 (0 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
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# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
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# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
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# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
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#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register,
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* and SPI Interrupt Mask Register (common bit fields)
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*/
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#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
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#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
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#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */
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#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SPI_INT_ENDRX (1 << 4) /* Bit 4: End of RX buffer */
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# define SPI_INT_ENDTX (1 << 5) /* Bit 5: End of TX buffer */
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# define SPI_INT_RXBUFF (1 << 6) /* Bit 6: RX Buffer Full */
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# define SPI_INT_TXBUFE (1 << 7) /* Bit 7: TX Buffer Empty */
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#endif
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#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
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#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
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#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
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#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
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/* SPI Chip Select Registers 0-3 */
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#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
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#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
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#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */
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#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */
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#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
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#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT)
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# define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */
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# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */
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# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */
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# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */
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# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */
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# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */
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# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */
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# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */
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# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */
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# define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */
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#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
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#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT)
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# define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT)
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#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */
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#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT)
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# define SPI_CSR_DLYBS(n) ((uint32_t)(n) << SPI_CSR_DLYBS_SHIFT)
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#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
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#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT)
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# define SPI_CSR_DLYBCT(n) ((uint32_t)(n) << SPI_CSR_DLYBCT_SHIFT)
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/* SPI Write Protection Control Register */
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#define SPI_WPCR_WPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */
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#define SPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
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#define SPI_WPCR_WPKEY_MASK (0x00ffffff << SPI_WPCR_WPKEY_SHIFT)
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# define SPI_WPCR_WPKEY (0x00535049 << SPI_WPCR_WPKEY_SHIFT)
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/* SPI Write Protection Status Register */
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SPI_WPSR_WPVS (1 << 0) /* Bit 0: SPI Write Protection Violation Status */
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#else
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# define SPI_WPSR_WPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */
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# define SPI_WPSR_WPVS_MASK (7 << SPI_WPSR_WPVS_SHIFT)
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#endif
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#define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
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#define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT)
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/* Features Register */
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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# define SPI_FEATURES_NCS_SHIFT (0) /* Bits 0-3: Number of Chip Selects */
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# define SPI_FEATURES_NCS_MASK (15 << SPI_FEATURES_NCS_SHIFT)
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# define SPI_FEATURES_PCONF (1 << 4) /* Bit 4: Polarity Configurable */
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# define SPI_FEATURES_PPNCONF (1 << 5) /* Bit 5: Polarity Positive if Polarity not Configurable */
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# define SPI_FEATURES_PHCONF (1 << 6) /* Bit 6: Phase Configurable */
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# define SPI_FEATURES_PHZNCONF (1 << 7) /* Bit 7: Phase is Zero if Phase not Configurable */
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# define SPI_FEATURES_LENCONF (1 << 8) /* Bit 8: Character Length Configurable */
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# define SPI_FEATURES_LENNCONF_SHIFT (9) /* Bits 9-15: Character Length if not Configurable */
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# define SPI_FEATURES_LENNCONF_MASK (0x7f << SPI_FEATURES_LENNCONF_SHIFT)
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# define SPI_FEATURES_EXTDEC (1 << 16) /* Bit 16: External Decoder True */
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# define SPI_FEATURES_CSNAATIMPL (1 << 17) /* Bit 17: CSNAAT Features Implemented */
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# define SPI_FEATURES_BRPBHSB (1 << 18) /* Bit 18: Bridge Type is PB to HSB */
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# define SPI_FEATURES_FIFORIMPL (1 << 19) /* Bit 19: FIFO in Reception Implemented */
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# define SPI_FEATURES_SWIMPL (1 << 20) /* Bit 20: Spurious Write Protection Implemented */
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#endif
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/* Version Register */
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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# define SPI_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Module version number */
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# define SPI_VERSION_VERSION_MASK (0xfff << SPI_VERSION_VERSION_SHIFT)
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# define SPI_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved */
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# define SPI_VERSION_MFN_MASK (7 << SPI_VERSION_MFN_SHIFT)
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#endif
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H */
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