68 lines
3.0 KiB
C
68 lines
3.0 KiB
C
/****************************************************************************
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* arch/arm/src/imx1/imx_wdog.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMX1_IMX_WDOG_H
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#define __ARCH_ARM_SRC_IMX1_IMX_WDOG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* WDOG Register Offsets ****************************************************/
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#define WDOG_WCR_OFFSET 0x0000 /* Watchdog Control Register */
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#define WDOG_WSR_OFFSET 0x0004 /* Watchdog Service Register */
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#define WDOG_WSTR_OFFSET 0x0008 /* Watchdog Status Register */
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/* WDOG Register Addresses **************************************************/
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#define IMX_WDOG_WCR (IMX_WDOG_VBASE + WDOG_WCR_OFFSET)
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#define IMX_WDOG_WSR (IMX_WDOG_VBASE + WDOG_WSR_OFFSET)
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#define IMX_WDOG_WSTRT (IMX_WDOG_VBASE + WDOG_WSTR_OFFSET)
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/* WDOG Register Bit Definitions ********************************************/
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/* Watchdog Control Register */
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#define WDOG_WCR_WDE (1 << 0) /* Bit 0: Watchdog Enable */
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#define WDOG_WCR_WDEC (1 << 1) /* Bit 1: Watchdog Enable Control */
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#define WDOG_WCR_SWR (1 << 2) /* Bit 2: Software Reset Enable */
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#define WDOG_WCR_TMD (1 << 3) /* Bit 3: Test Mode Enable */
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#define WDOG_WCR_WIE (1 << 4) /* Bit 4: Watchdog Interrupt Enable */
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#define WDOG_WCR_WT_SHIFT 8 /* Bit 8-14: Watchdog Timeout */
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#define WDOG_WCR_WT_MASK (0x7f << WDOG_WCR_WT_SHIFT)
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#define WDOG_WCR_WHALT (1 << 15) /* Bit 15: Watchdog Halt */
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/* Watchdog Service Register */
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#define WDOG_WSR_SHIFT 0 /* Bit 0-15: Watchdog Service Register */
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#define WDOG_WT_MASK (0xffff << WDOG_WSR_SHIFT)
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_IMX1_IMX_WDOG_H */
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