6695affe87
The number of exception for risc-v is 16 (0 ~ 15) for the machine ISA version 1.12 or earlier, the number of exception is 20 (0 ~ 19) from the ISA version 1.13. And maybe changed in the future. Using a dedicated option to control the exception number to allow the earlier version chip with customized exception number (e.g. 16 ~ 19 used) to define the exception reason string correctly. Signed-off-by: Huang Qi <huangqi3@xiaomi.com> |
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arm | ||
arm64 | ||
avr | ||
ceva | ||
dummy | ||
hc | ||
mips | ||
misoc | ||
or1k | ||
renesas | ||
risc-v | ||
sim | ||
sparc | ||
tricore | ||
x86 | ||
x86_64 | ||
xtensa | ||
z16 | ||
z80 | ||
CMakeLists.txt | ||
Kconfig |