218 lines
10 KiB
C
218 lines
10 KiB
C
/****************************************************************************
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* boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Most of the settings within this file derives from NXP sample code for
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* the S32K1XX MCUs. That sample code has this licensing information:
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*
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* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "s32k1xx_clockconfig.h"
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#include "s32k1xx_start.h"
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#include "s32k146evb.h"
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Each S32K1XX board must provide the following initialized structure.
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* This is needed to establish the initial board clocking.
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*/
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const struct clock_configuration_s g_initial_clkconfig =
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{
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.scg =
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{
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.sirc =
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{
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.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = false, /* SIRCSTEN */
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.lowpower = true, /* SIRCLPEN */
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.locked = false, /* LK */
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},
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.firc =
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{
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.range = SCG_FIRC_RANGE_48M, /* RANGE */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
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.initialize = true, /* Initialize */
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.regulator = true, /* FIRCREGOFF */
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.locked = false, /* LK */
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},
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.sosc =
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{
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.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
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.gain = SCG_SOSC_GAIN_LOW, /* HGO */
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.range = SCG_SOSC_RANGE_HIGH, /* RANGE */
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.extref = SCG_SOSC_REF_OSC, /* EREFS */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
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.initialize = true, /* Initialize */
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.locked = false, /* LK */
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},
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.spll =
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{
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.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
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.prediv = 1, /* PREDIV */
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.mult = 40, /* MULT */
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.src = 0, /* SOURCE */
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.initialize = true, /* Initialize */
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.locked = false, /* LK */
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},
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.rtc =
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{
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.initialize = true, /* Initialize */
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.clkin = 0, /* RTC_CLKIN */
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},
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.clockout =
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{
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.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
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.initialize = true, /* Initialize */
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},
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.clockmode =
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{
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.rccr = /* RCCR - Run Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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.vccr = /* VCCR - VLPR Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
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.divslow = 4, /* DIVSLOW, range 1..16 */
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.divbus = 1, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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.hccr =
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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.initialize = true, /* Initialize */
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},
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},
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.sim =
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{
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.clockout = /* Clock Out configuration. */
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{
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.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
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.divider = 1, /* CLKOUTDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = false, /* CLKOUTEN */
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},
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.lpoclk = /* Low Power Clock configuration. */
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{
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.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
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.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
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.initialize = true, /* Initialize */
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.lpo32k = true, /* LPO32KCLKEN */
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.lpo1k = true, /* LPO1KCLKEN */
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},
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.tclk = /* TCLK CLOCK configuration. */
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{
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.tclkfreq[0] = 0, /* TCLK0 */
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.tclkfreq[1] = 0, /* TCLK1 */
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.tclkfreq[2] = 0, /* TCLK2 */
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.initialize = true, /* Initialize */
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},
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.platgate = /* Platform Gate Clock configuration. */
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{
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.initialize = true, /* Initialize */
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.mscm = true, /* CGCMSCM */
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.mpu = true, /* CGCMPU */
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.dma = true, /* CGCDMA */
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.erm = true, /* CGCERM */
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.eim = true, /* CGCEIM */
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},
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.traceclk = /* Debug trace Clock Configuration. */
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{
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.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
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.divider = 1, /* TRACEDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = true, /* TRACEDIVEN */
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.fraction = false, /* TRACEFRAC */
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},
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},
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.pcc =
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{
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.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
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.pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */
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},
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.pmc =
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{
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.lpoclk = /* Low Power Clock configuration. */
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{
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.trim = 0, /* Trimming value for LPO */
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.initialize = true, /* Initialize */
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.enable = true, /* Enable/disable LPO */
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},
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},
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};
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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