319 lines
20 KiB
C
319 lines
20 KiB
C
/****************************************************************************
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* arch/arm/include/lc823450/irq.h
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*
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* Copyright 2014,2015,2016,2017 Sony Video & Sound Products Inc.
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* Author: Masatoshi Tateishi <Masatoshi.Tateishi@jp.sony.com>
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* Author: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_LC823450_IRQ_H
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#define __ARCH_ARM_INCLUDE_LC823450_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*/
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/* Processor Exceptions (vectors 0-15) */
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#define LC823450_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define LC823450_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define LC823450_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define LC823450_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define LC823450_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define LC823450_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define LC823450_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define LC823450_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define LC823450_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define LC823450_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are chip-specific */
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#define LC823450_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/lc823450/irq.h
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*
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* External interrupts (vectors >= 16)
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*/
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#define LC823450_IRQ_CTXM3_00 (LC823450_IRQ_INTERRUPTS+0) /* 16: CortexM3_00 interrupt */
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#define LC823450_IRQ_CTXM3_01 (LC823450_IRQ_INTERRUPTS+1) /* 17: CortexM3_01 interrupt */
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#define LC823450_IRQ_CTXM3_02 (LC823450_IRQ_INTERRUPTS+2) /* 18: CortexM3_02 interrupt */
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#define LC823450_IRQ_CTXM3_03 (LC823450_IRQ_INTERRUPTS+3) /* 19: CortexM3_03 interrupt */
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#define LC823450_IRQ_CTXM3_10 (LC823450_IRQ_INTERRUPTS+4) /* 20: CortexM3_00 interrupt */
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#define LC823450_IRQ_CTXM3_11 (LC823450_IRQ_INTERRUPTS+5) /* 21: CortexM3_01 interrupt */
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#define LC823450_IRQ_CTXM3_12 (LC823450_IRQ_INTERRUPTS+6) /* 22: CortexM3_02 interrupt */
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#define LC823450_IRQ_CTXM3_13 (LC823450_IRQ_INTERRUPTS+7) /* 23: CortexM3_03 interrupt */
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#define LC823450_IRQ_LPDSP0 (LC823450_IRQ_INTERRUPTS+8) /* 24: LPDSP0 interrupt */
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#define LC823450_IRQ_LPDSP1 (LC823450_IRQ_INTERRUPTS+9) /* 25: LPDSP1 interrupt */
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#define LC823450_IRQ_LPDSP2 (LC823450_IRQ_INTERRUPTS+10) /* 26: LPDSP2 interrupt */
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#define LC823450_IRQ_LPDSP3 (LC823450_IRQ_INTERRUPTS+11) /* 27: LPDSP3 interrupt */
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#define LC823450_IRQ_WDT0 (LC823450_IRQ_INTERRUPTS+12) /* 28: WatchDogTimer0 interrupt */
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#define LC823450_IRQ_WDT1 (LC823450_IRQ_INTERRUPTS+13) /* 29: WatchDogTimer1 interrupt */
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#define LC823450_IRQ_WDT2 (LC823450_IRQ_INTERRUPTS+14) /* 30: WatchDogTimer2 interrupt */
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#define LC823450_IRQ_BTIMER0 (LC823450_IRQ_INTERRUPTS+15) /* 31: BasicTimer0 interrupt */
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#define LC823450_IRQ_BTIMER1 (LC823450_IRQ_INTERRUPTS+16) /* 32: BasicTimer0 interrupt */
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#define LC823450_IRQ_BTIMER2 (LC823450_IRQ_INTERRUPTS+17) /* 33: BasicTimer0 interrupt */
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#define LC823450_IRQ_MTIMER00 (LC823450_IRQ_INTERRUPTS+18) /* 34: MultipleTimer00 interrupt */
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#define LC823450_IRQ_MTIMER01 (LC823450_IRQ_INTERRUPTS+19) /* 35: MultipleTimer01 interrupt */
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#define LC823450_IRQ_MTIMER10 (LC823450_IRQ_INTERRUPTS+20) /* 36: MultipleTimer10 interrupt */
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#define LC823450_IRQ_MTIMER11 (LC823450_IRQ_INTERRUPTS+21) /* 37: MultipleTimer11 interrupt */
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#define LC823450_IRQ_MTIMER20 (LC823450_IRQ_INTERRUPTS+22) /* 38: MultipleTimer20 interrupt */
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#define LC823450_IRQ_MTIMER21 (LC823450_IRQ_INTERRUPTS+23) /* 39: MultipleTimer21 interrupt */
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#define LC823450_IRQ_MTIMER30 (LC823450_IRQ_INTERRUPTS+24) /* 40: MultipleTimer30 interrupt */
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#define LC823450_IRQ_MTIMER31 (LC823450_IRQ_INTERRUPTS+25) /* 41: MultipleTimer31 interrupt */
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#define LC823450_IRQ_EHCI (LC823450_IRQ_INTERRUPTS+26) /* 42: USB HOST EHCI interrupt */
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#define LC823450_IRQ_OHCI (LC823450_IRQ_INTERRUPTS+27) /* 43: USB HOST OHCI interrupt */
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#define LC823450_IRQ_SERFLASH (LC823450_IRQ_INTERRUPTS+28) /* 44: USB HOST OHCI interrupt */
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#define LC823450_IRQ_DMAC (LC823450_IRQ_INTERRUPTS+29) /* 45: DMA Controller interrupt */
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#define LC823450_IRQ_SDCSYNC0 (LC823450_IRQ_INTERRUPTS+30) /* 46: SDCardSync0 interrupt */
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#define LC823450_IRQ_SDCSYNC1 (LC823450_IRQ_INTERRUPTS+31) /* 47: SDCardSync1 interrupt */
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#define LC823450_IRQ_SDCSYNC2 (LC823450_IRQ_INTERRUPTS+32) /* 48: SDCardSync2 interrupt */
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#define LC823450_IRQ_SDCASYNC0 (LC823450_IRQ_INTERRUPTS+33) /* 49: SDCardAsync0 interrupt */
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#define LC823450_IRQ_SDCASYNC1 (LC823450_IRQ_INTERRUPTS+34) /* 50: SDCardAsync1 interrupt */
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#define LC823450_IRQ_SDCASYNC2 (LC823450_IRQ_INTERRUPTS+35) /* 51: SDCardAsync2 interrupt */
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#define LC823450_IRQ_MEMSTICK (LC823450_IRQ_INTERRUPTS+36) /* 52: MemoryStick interrupt */
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#define LC823450_IRQ_MEMSTICKINS (LC823450_IRQ_INTERRUPTS+37) /* 53: MemoryStick ins interrupt */
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#define LC823450_IRQ_DSPCMD (LC823450_IRQ_INTERRUPTS+38) /* 54: DSP cmd interface interrupt */
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#define LC823450_IRQ_ADC (LC823450_IRQ_INTERRUPTS+39) /* 55: AD Converter interrupt */
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#define LC823450_IRQ_SIO (LC823450_IRQ_INTERRUPTS+40) /* 56: SIO interrupt */
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#define LC823450_IRQ_I2C0 (LC823450_IRQ_INTERRUPTS+41) /* 57: I2C0 interrupt */
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#define LC823450_IRQ_I2C1 (LC823450_IRQ_INTERRUPTS+42) /* 58: I2C1 interrupt */
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#define LC823450_IRQ_UART0 (LC823450_IRQ_INTERRUPTS+43) /* 59: UART0 interrupt */
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#define LC823450_IRQ_UART1 (LC823450_IRQ_INTERRUPTS+44) /* 60: UART1 interrupt */
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#define LC823450_IRQ_UART2 (LC823450_IRQ_INTERRUPTS+45) /* 61: UART2 interrupt */
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#define LC823450_IRQ_RTC (LC823450_IRQ_INTERRUPTS+46) /* 62: RTC interrupt */
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#define LC823450_IRQ_RTCKEY (LC823450_IRQ_INTERRUPTS+47) /* 63: RTCKEY interrupt */
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#define LC823450_IRQ_AUDIOBUF0 (LC823450_IRQ_INTERRUPTS+48) /* 64: AudioBuffer0 interrupt */
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#define LC823450_IRQ_AUDIOBUF1 (LC823450_IRQ_INTERRUPTS+49) /* 65: AudioBuffer1 interrupt */
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#define LC823450_IRQ_AUDIOBUF2 (LC823450_IRQ_INTERRUPTS+50) /* 66: AudioBuffer2 interrupt */
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#define LC823450_IRQ_AUDIOBUF3 (LC823450_IRQ_INTERRUPTS+51) /* 67: AudioBuffer3 interrupt */
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#define LC823450_IRQ_AUDIOSTAT0 (LC823450_IRQ_INTERRUPTS+52) /* 68: AudioStatus0 interrupt */
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#define LC823450_IRQ_AUDIOSTAT1 (LC823450_IRQ_INTERRUPTS+53) /* 69: AudioStatus1 interrupt */
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#define LC823450_IRQ_AUDIOSTAT2 (LC823450_IRQ_INTERRUPTS+54) /* 70: AudioStatus2 interrupt */
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#define LC823450_IRQ_AUDIOSTAT3 (LC823450_IRQ_INTERRUPTS+55) /* 71: AudioStatus3 interrupt */
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#define LC823450_IRQ_AUDIOTM0 (LC823450_IRQ_INTERRUPTS+56) /* 72: AudioTimer0 interrupt */
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#define LC823450_IRQ_AUDIOTM1 (LC823450_IRQ_INTERRUPTS+57) /* 73: AudioTimer1 interrupt */
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#define LC823450_IRQ_USBDEV (LC823450_IRQ_INTERRUPTS+58) /* 74: USB Device interrupt */
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#define LC823450_IRQ_EXTINT0 (LC823450_IRQ_INTERRUPTS+59) /* 75: ExternalINT0 interrupt */
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#define LC823450_IRQ_EXTINT1 (LC823450_IRQ_INTERRUPTS+60) /* 76: ExternalINT1 interrupt */
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#define LC823450_IRQ_EXTINT2 (LC823450_IRQ_INTERRUPTS+61) /* 77: ExternalINT2 interrupt */
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#define LC823450_IRQ_EXTINT3 (LC823450_IRQ_INTERRUPTS+62) /* 78: ExternalINT3 interrupt */
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#define LC823450_IRQ_EXTINT4 (LC823450_IRQ_INTERRUPTS+63) /* 79: ExternalINT4 interrupt */
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#define LC823450_IRQ_EXTINT5 (LC823450_IRQ_INTERRUPTS+64) /* 80: ExternalINT5 interrupt */
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#define LC823450_IRQ_NEXTINT (65)
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#define LC823450_IRQ_NIRQS (LC823450_IRQ_EXTINT5 + 1)
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#define LC823450_IRQ_GPIO00 (LC823450_IRQ_NIRQS + 0) /* 81: GPIO00 */
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#define LC823450_IRQ_GPIO01 (LC823450_IRQ_NIRQS + 1) /* 82: GPIO01 */
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#define LC823450_IRQ_GPIO02 (LC823450_IRQ_NIRQS + 2) /* 83: GPIO02 */
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#define LC823450_IRQ_GPIO03 (LC823450_IRQ_NIRQS + 3) /* 84: GPIO03 */
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#define LC823450_IRQ_GPIO04 (LC823450_IRQ_NIRQS + 4) /* 85: GPIO04 */
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#define LC823450_IRQ_GPIO05 (LC823450_IRQ_NIRQS + 5) /* 86: GPIO05 */
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#define LC823450_IRQ_GPIO06 (LC823450_IRQ_NIRQS + 6) /* 87: GPIO06 */
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#define LC823450_IRQ_GPIO07 (LC823450_IRQ_NIRQS + 7) /* 88: GPIO07 */
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#define LC823450_IRQ_GPIO08 (LC823450_IRQ_NIRQS + 8) /* 89: GPIO08 */
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#define LC823450_IRQ_GPIO09 (LC823450_IRQ_NIRQS + 9) /* 90: GPIO09 */
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#define LC823450_IRQ_GPIO0A (LC823450_IRQ_NIRQS + 10) /* 91: GPIO0A */
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#define LC823450_IRQ_GPIO0B (LC823450_IRQ_NIRQS + 11) /* 92: GPIO0B */
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#define LC823450_IRQ_GPIO0C (LC823450_IRQ_NIRQS + 12) /* 93: GPIO0C */
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#define LC823450_IRQ_GPIO0D (LC823450_IRQ_NIRQS + 13) /* 94: GPIO0D */
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#define LC823450_IRQ_GPIO0E (LC823450_IRQ_NIRQS + 14) /* 95: GPIO0E */
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#define LC823450_IRQ_GPIO0F (LC823450_IRQ_NIRQS + 15) /* 96: GPIO0F */
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#define LC823450_IRQ_GPIO10 (LC823450_IRQ_NIRQS + 16) /* 97: GPIO10 */
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#define LC823450_IRQ_GPIO11 (LC823450_IRQ_NIRQS + 17) /* 98: GPIO11 */
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#define LC823450_IRQ_GPIO12 (LC823450_IRQ_NIRQS + 18) /* 99: GPIO12 */
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#define LC823450_IRQ_GPIO13 (LC823450_IRQ_NIRQS + 19) /* 100: GPIO13 */
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#define LC823450_IRQ_GPIO14 (LC823450_IRQ_NIRQS + 20) /* 101: GPIO14 */
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#define LC823450_IRQ_GPIO15 (LC823450_IRQ_NIRQS + 21) /* 102: GPIO15 */
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#define LC823450_IRQ_GPIO16 (LC823450_IRQ_NIRQS + 22) /* 103: GPIO16 */
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#define LC823450_IRQ_GPIO17 (LC823450_IRQ_NIRQS + 23) /* 104: GPIO17 */
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#define LC823450_IRQ_GPIO18 (LC823450_IRQ_NIRQS + 24) /* 105: GPIO18 */
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#define LC823450_IRQ_GPIO19 (LC823450_IRQ_NIRQS + 25) /* 106: GPIO19 */
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#define LC823450_IRQ_GPIO1A (LC823450_IRQ_NIRQS + 26) /* 107: GPIO1A */
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#define LC823450_IRQ_GPIO1B (LC823450_IRQ_NIRQS + 27) /* 108: GPIO1B */
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#define LC823450_IRQ_GPIO1C (LC823450_IRQ_NIRQS + 28) /* 109: GPIO1C */
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#define LC823450_IRQ_GPIO1D (LC823450_IRQ_NIRQS + 29) /* 110: GPIO1D */
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#define LC823450_IRQ_GPIO1E (LC823450_IRQ_NIRQS + 30) /* 111: GPIO1E */
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#define LC823450_IRQ_GPIO1F (LC823450_IRQ_NIRQS + 31) /* 112: GPIO1F */
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#define LC823450_IRQ_GPIO20 (LC823450_IRQ_NIRQS + 32) /* 113: GPIO20 */
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#define LC823450_IRQ_GPIO21 (LC823450_IRQ_NIRQS + 33) /* 114: GPIO21 */
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#define LC823450_IRQ_GPIO22 (LC823450_IRQ_NIRQS + 34) /* 115: GPIO22 */
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#define LC823450_IRQ_GPIO23 (LC823450_IRQ_NIRQS + 35) /* 116: GPIO23 */
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#define LC823450_IRQ_GPIO24 (LC823450_IRQ_NIRQS + 36) /* 117: GPIO24 */
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#define LC823450_IRQ_GPIO25 (LC823450_IRQ_NIRQS + 37) /* 118: GPIO25 */
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#define LC823450_IRQ_GPIO26 (LC823450_IRQ_NIRQS + 38) /* 119: GPIO26 */
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#define LC823450_IRQ_GPIO27 (LC823450_IRQ_NIRQS + 39) /* 120: GPIO27 */
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#define LC823450_IRQ_GPIO28 (LC823450_IRQ_NIRQS + 40) /* 121: GPIO28 */
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#define LC823450_IRQ_GPIO29 (LC823450_IRQ_NIRQS + 41) /* 122: GPIO29 */
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#define LC823450_IRQ_GPIO2A (LC823450_IRQ_NIRQS + 42) /* 123: GPIO2A */
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#define LC823450_IRQ_GPIO2B (LC823450_IRQ_NIRQS + 43) /* 124: GPIO2B */
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#define LC823450_IRQ_GPIO2C (LC823450_IRQ_NIRQS + 44) /* 125: GPIO2C */
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#define LC823450_IRQ_GPIO2D (LC823450_IRQ_NIRQS + 45) /* 126: GPIO2D */
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#define LC823450_IRQ_GPIO2E (LC823450_IRQ_NIRQS + 46) /* 127: GPIO2E */
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#define LC823450_IRQ_GPIO2F (LC823450_IRQ_NIRQS + 47) /* 128: GPIO2F */
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#define LC823450_IRQ_GPIO30 (LC823450_IRQ_NIRQS + 48) /* 129: GPIO30 */
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#define LC823450_IRQ_GPIO31 (LC823450_IRQ_NIRQS + 49) /* 130: GPIO31 */
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#define LC823450_IRQ_GPIO32 (LC823450_IRQ_NIRQS + 50) /* 131: GPIO32 */
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#define LC823450_IRQ_GPIO33 (LC823450_IRQ_NIRQS + 51) /* 132: GPIO33 */
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#define LC823450_IRQ_GPIO34 (LC823450_IRQ_NIRQS + 52) /* 133: GPIO34 */
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#define LC823450_IRQ_GPIO35 (LC823450_IRQ_NIRQS + 53) /* 134: GPIO35 */
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#define LC823450_IRQ_GPIO36 (LC823450_IRQ_NIRQS + 54) /* 135: GPIO36 */
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#define LC823450_IRQ_GPIO37 (LC823450_IRQ_NIRQS + 55) /* 136: GPIO37 */
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#define LC823450_IRQ_GPIO38 (LC823450_IRQ_NIRQS + 56) /* 137: GPIO38 */
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#define LC823450_IRQ_GPIO39 (LC823450_IRQ_NIRQS + 57) /* 138: GPIO39 */
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#define LC823450_IRQ_GPIO3A (LC823450_IRQ_NIRQS + 58) /* 139: GPIO3A */
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#define LC823450_IRQ_GPIO3B (LC823450_IRQ_NIRQS + 59) /* 140: GPIO3B */
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#define LC823450_IRQ_GPIO3C (LC823450_IRQ_NIRQS + 60) /* 141: GPIO3C */
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#define LC823450_IRQ_GPIO3D (LC823450_IRQ_NIRQS + 61) /* 142: GPIO3D */
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#define LC823450_IRQ_GPIO3E (LC823450_IRQ_NIRQS + 62) /* 143: GPIO3E */
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#define LC823450_IRQ_GPIO3F (LC823450_IRQ_NIRQS + 63) /* 144: GPIO3F */
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#define LC823450_IRQ_GPIO40 (LC823450_IRQ_NIRQS + 64) /* 145: GPIO40 */
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#define LC823450_IRQ_GPIO41 (LC823450_IRQ_NIRQS + 65) /* 146: GPIO41 */
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#define LC823450_IRQ_GPIO42 (LC823450_IRQ_NIRQS + 66) /* 147: GPIO42 */
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#define LC823450_IRQ_GPIO43 (LC823450_IRQ_NIRQS + 67) /* 148: GPIO43 */
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#define LC823450_IRQ_GPIO44 (LC823450_IRQ_NIRQS + 68) /* 149: GPIO44 */
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#define LC823450_IRQ_GPIO45 (LC823450_IRQ_NIRQS + 69) /* 150: GPIO45 */
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#define LC823450_IRQ_GPIO46 (LC823450_IRQ_NIRQS + 70) /* 151: GPIO46 */
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#define LC823450_IRQ_GPIO47 (LC823450_IRQ_NIRQS + 71) /* 152: GPIO47 */
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#define LC823450_IRQ_GPIO48 (LC823450_IRQ_NIRQS + 72) /* 153: GPIO48 */
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#define LC823450_IRQ_GPIO49 (LC823450_IRQ_NIRQS + 73) /* 154: GPIO49 */
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#define LC823450_IRQ_GPIO4A (LC823450_IRQ_NIRQS + 74) /* 155: GPIO4A */
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#define LC823450_IRQ_GPIO4B (LC823450_IRQ_NIRQS + 75) /* 156: GPIO4B */
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#define LC823450_IRQ_GPIO4C (LC823450_IRQ_NIRQS + 76) /* 157: GPIO4C */
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#define LC823450_IRQ_GPIO4D (LC823450_IRQ_NIRQS + 77) /* 158: GPIO4D */
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#define LC823450_IRQ_GPIO4E (LC823450_IRQ_NIRQS + 78) /* 159: GPIO4E */
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#define LC823450_IRQ_GPIO4F (LC823450_IRQ_NIRQS + 79) /* 160: GPIO4F */
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#define LC823450_IRQ_GPIO50 (LC823450_IRQ_NIRQS + 80) /* 161: GPIO50 */
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#define LC823450_IRQ_GPIO51 (LC823450_IRQ_NIRQS + 81) /* 162: GPIO51 */
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#define LC823450_IRQ_GPIO52 (LC823450_IRQ_NIRQS + 82) /* 163: GPIO52 */
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#define LC823450_IRQ_GPIO53 (LC823450_IRQ_NIRQS + 83) /* 164: GPIO53 */
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#define LC823450_IRQ_GPIO54 (LC823450_IRQ_NIRQS + 84) /* 165: GPIO54 */
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#define LC823450_IRQ_GPIO55 (LC823450_IRQ_NIRQS + 85) /* 166: GPIO55 */
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#define LC823450_IRQ_GPIO56 (LC823450_IRQ_NIRQS + 86) /* 167: GPIO56 */
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#define LC823450_IRQ_GPIO57 (LC823450_IRQ_NIRQS + 87) /* 168: GPIO57 */
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#define LC823450_IRQ_GPIO58 (LC823450_IRQ_NIRQS + 88) /* 169: GPIO58 */
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#define LC823450_IRQ_GPIO59 (LC823450_IRQ_NIRQS + 89) /* 170: GPIO59 */
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#define LC823450_IRQ_NGPIOIRQS (90)
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#ifdef CONFIG_LC823450_VIRQ
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#define LC823450_IRQ_VIRTUAL (LC823450_IRQ_NIRQS + LC823450_IRQ_NGPIOIRQS)
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#define LC823450_IRQ_V00 (LC823450_IRQ_VIRTUAL + 0) /* 171: V00 */
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#define LC823450_IRQ_NVIRTUALIRQS (1)
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#else /* CONFIG_LC823450_VIRQ */
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#define LC823450_IRQ_NVIRTUALIRQS (0)
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#endif /* CONFIG_LC823450_VIRQ */
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#define NR_IRQS (LC823450_IRQ_NIRQS + LC823450_IRQ_NGPIOIRQS + \
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LC823450_IRQ_NVIRTUALIRQS)
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/****************************************************************************
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* Public Types
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|
****************************************************************************/
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|
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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enum lc823450_srctype_e
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{
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SRCTYPE_FALLING = 0, /* Falling edge */
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SRCTYPE_LOW, /* Low level */
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SRCTYPE_RISING, /* Rigsing edge */
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SRCTYPE_HIGH, /* High level */
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SRCTYPE_MAX,
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};
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#ifdef CONFIG_LC823450_VIRQ
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struct lc823450_irq_ops {
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void (*enable)(int irq);
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void (*disable)(int irq);
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int (*srctype)(int irq, enum lc823450_srctype_e type);
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};
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#endif /* CONFIG_LC823450_VIRQ */
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|
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#endif
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|
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/****************************************************************************
|
|
* Public Data
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
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|
#ifdef __cplusplus
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|
#define EXTERN extern "C"
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|
extern "C" {
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|
#else
|
|
#define EXTERN extern
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|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
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EXTERN int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype);
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|
#ifdef CONFIG_LC823450_VIRQ
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|
EXTERN int lc823450_irq_register(int irq, struct lc823450_irq_ops *ops);
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|
#endif /* CONFIG_LC823450_VIRQ */
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|
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* __ARCH_ARM_INCLUDE_LC823450_IRQ_H */
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