51b20403c6
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5585 42af7a65-404d-4744-a932-0658087f49c3
172 lines
8.9 KiB
C
172 lines
8.9 KiB
C
/************************************************************************************
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* arch/arm/include/lm/chip.h
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*
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* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Jose Pablo Carballo <jcarballo@nx-engineering.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LM_CHIP_H
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#define __ARCH_ARM_INCLUDE_LM_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
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#if defined(CONFIG_ARCH_CHIP_LM3S6918)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 2 /* Two SSI modules */
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# define LM_NUARTS 2 /* Two UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 0 /* No PWM generator modules */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 3 /* Three general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 2 /* Two UART modules */
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# define LM_NI2C 1 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 1 /* One PWM generator module */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 3 /* Three UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 3 /* Three PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 2 /* Two SSI modules */
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# define LM_NUARTS 3 /* Three UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 2 /* Two ADC module */
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# define LM_CAN 2 /* Two CAN module */
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# define LM_NPWM 4 /* Four PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 6 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 3 /* Two UART modules */
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# define LM_NI2C 2 /* One I2C module */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 3 /* Three PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
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# define LM_NCANCONTROLLER 1 /* One CAN controller */
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#elif defined(CONFIG_ARCH_CHIP_LM4F120)
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# undef LM3S /* Not LM3S family */
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# define LM4F 1 /* LM4F family */
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# define LM_NTIMERS 6 /* Six general purpose timers */
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# define LM_NWIDETIMERS 6 /* Six general purpose wide timers */
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# define LM_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define LM_NSSI 4 /* Four SSI module */
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# define LM_NUARTS 8 /* Eight UART modules */
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# define LM_NI2C 4 /* Four I2C modules */
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# define LM_NADC 2 /* Two ADC modules */
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# define LM_NPWM 0 /* No PWM generator modules */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
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# define LM_NCANCONTROLLER 1 /* One CAN controller */
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#else
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# error "Capabilities not specified for this Stellaris chip"
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#endif
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/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism
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* will only look at the upper N bits of the 8-bit priority level (where N is 3 for
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* the Stellaris family), so any prioritization must be performed in those bits.
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* The default priority level is set to the middle value
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [5:7] set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */
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#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_LM_CHIP_H */
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