69fd539886
Invalidate operations at DDI0246H_l2c310_r3p3_trm: If there is a stale entry in the L2 cache, the system enables the invalidation of the L1 cache. But before the controller invalidates the L2 cache, it allocates a line from the L2 cache to an L1 cache. The robust code sequence for invalidation with a non-exclusive cache arrangement is: 1. InvalLevel2 Address ; forces the address out past level 2 2. CACHE SYNC ; Ensures completion of the L2 inval 3. InvalLevel1 Address ; This is broadcast within the cluster 4. DSB ; Ensure completion of the inval as far as Level 2. This sequence ensures that, if there is an allocation to L1 after the L1 invalidation, the data picked up is the new data and not stale data from the L2 Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com> |
||
|---|---|---|
| .. | ||
| include | ||
| src | ||
| Kconfig | ||