6a3c2aded6
* Simplify EINTR/ECANCEL error handling 1. Add semaphore uninterruptible wait function 2 .Replace semaphore wait loop with a single uninterruptible wait 3. Replace all sem_xxx to nxsem_xxx * Unify the void cast usage 1. Remove void cast for function because many place ignore the returned value witout cast 2. Replace void cast for variable with UNUSED macro
341 lines
8.4 KiB
C
341 lines
8.4 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32_aes.c
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*
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* Copyright (C) 2015 Haltian Ltd. All rights reserved.
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* Author: Juha Niskanen <juha.niskanen@haltian.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/crypto/crypto.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32_rcc.h"
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#include "stm32_aes.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define AES_BLOCK_SIZE 16
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static void stm32aes_enable(bool on);
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static void stm32aes_ccfc(void);
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static void stm32aes_setkey(FAR const void *key, size_t key_len);
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static void stm32aes_setiv(FAR const void *iv);
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static void stm32aes_encryptblock(FAR void *block_out,
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FAR const void *block_in);
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static int stm32aes_setup_cr(int mode, int encrypt);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static sem_t g_stm32aes_lock;
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static bool g_stm32aes_initdone = false;
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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static void stm32aes_enable(bool on)
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{
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uint32_t regval;
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regval = getreg32(STM32_AES_CR);
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if (on)
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{
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regval |= AES_CR_EN;
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}
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else
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{
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regval &= ~AES_CR_EN;
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}
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putreg32(regval, STM32_AES_CR);
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}
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/* Clear AES_SR_CCF status register bit */
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static void stm32aes_ccfc(void)
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{
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uint32_t regval;
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regval = getreg32(STM32_AES_CR);
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regval |= AES_CR_CCFC;
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putreg32(regval, STM32_AES_CR);
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}
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/* TODO: Handle other AES key lengths or fail if length is not valid */
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static void stm32aes_setkey(FAR const void *key, size_t key_len)
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{
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FAR uint32_t *in = (FAR uint32_t *)key;
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putreg32(__builtin_bswap32(*in), STM32_AES_KEYR3);
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in++;
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putreg32(__builtin_bswap32(*in), STM32_AES_KEYR2);
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in++;
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putreg32(__builtin_bswap32(*in), STM32_AES_KEYR1);
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in++;
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putreg32(__builtin_bswap32(*in), STM32_AES_KEYR0);
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}
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static void stm32aes_setiv(FAR const void *iv)
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{
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FAR uint32_t *in = (FAR uint32_t *)iv;
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putreg32(__builtin_bswap32(*in), STM32_AES_IVR3);
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in++;
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putreg32(__builtin_bswap32(*in), STM32_AES_IVR2);
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in++;
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putreg32(__builtin_bswap32(*in), STM32_AES_IVR1);
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in++;
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putreg32(__builtin_bswap32(*in), STM32_AES_IVR0);
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}
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static void stm32aes_encryptblock(FAR void *block_out, FAR const void *block_in)
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{
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FAR uint32_t *in = (FAR uint32_t *)block_in;
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FAR uint32_t *out = (FAR uint32_t *)block_out;
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putreg32(*in, STM32_AES_DINR);
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in++;
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putreg32(*in, STM32_AES_DINR);
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in++;
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putreg32(*in, STM32_AES_DINR);
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in++;
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putreg32(*in, STM32_AES_DINR);
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while (!(getreg32(STM32_AES_SR) & AES_SR_CCF));
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stm32aes_ccfc();
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*out = getreg32(STM32_AES_DOUTR);
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out++;
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*out = getreg32(STM32_AES_DOUTR);
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out++;
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*out = getreg32(STM32_AES_DOUTR);
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out++;
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*out = getreg32(STM32_AES_DOUTR);
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}
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static int stm32aes_setup_cr(int mode, int encrypt)
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{
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uint32_t regval = 0;
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regval |= AES_CR_DATATYPE_BE;
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switch (mode)
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{
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case AES_MODE_ECB:
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regval |= AES_CR_CHMOD_ECB;
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break;
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case AES_MODE_CBC:
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regval |= AES_CR_CHMOD_CBC;
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break;
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case AES_MODE_CTR:
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regval |= AES_CR_CHMOD_CTR;
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break;
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default:
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return -EINVAL;
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}
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if (encrypt)
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{
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regval |= AES_CR_MODE_ENCRYPT;
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}
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else
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{
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if (mode == AES_MODE_CTR)
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{
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regval |= AES_CR_MODE_DECRYPT;
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}
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else
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{
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regval |= AES_CR_MODE_DECRYPT_KEYDERIV;
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}
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}
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putreg32(regval, STM32_AES_CR);
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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int stm32_aesreset(void)
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{
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irqstate_t flags;
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uint32_t regval;
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flags = enter_critical_section();
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regval = getreg32(STM32_RCC_AHBRSTR);
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regval |= RCC_AHBRSTR_AESRST;
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putreg32(regval, STM32_RCC_AHBRSTR);
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regval &= ~RCC_AHBRSTR_AESRST;
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putreg32(regval, STM32_RCC_AHBRSTR);
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leave_critical_section(flags);
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return OK;
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}
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int stm32_aesinitialize(void)
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{
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uint32_t regval;
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nxsem_init(&g_stm32aes_lock, 0, 1);
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regval = getreg32(STM32_RCC_AHBENR);
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regval |= RCC_AHBENR_AESEN;
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putreg32(regval, STM32_RCC_AHBENR);
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stm32aes_enable(false);
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return OK;
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}
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int stm32_aesuninitialize(void)
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{
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uint32_t regval;
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stm32aes_enable(false);
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regval = getreg32(STM32_RCC_AHBENR);
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regval &= ~RCC_AHBENR_AESEN;
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putreg32(regval, STM32_RCC_AHBENR);
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nxsem_destroy(&g_stm32aes_lock);
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return OK;
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}
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int aes_cypher(FAR void *out, FAR const void *in, uint32_t size,
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FAR const void *iv, FAR const void *key, uint32_t keysize,
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int mode, int encrypt)
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{
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int ret = OK;
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/* Ensure initialization was done */
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if (!g_stm32aes_initdone)
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{
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ret = stm32_aesinitialize();
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if (ret < 0)
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{
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return ret; /* AES init failed */
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}
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g_stm32aes_initdone = true;
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}
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if ((size & (AES_BLOCK_SIZE-1)) != 0)
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{
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return -EINVAL;
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}
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if (keysize != 16)
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{
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return -EINVAL;
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}
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ret = nxsem_wait(&g_stm32aes_lock);
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if (ret < 0)
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{
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return ret;
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}
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/* AES must be disabled before changing mode, key or IV. */
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stm32aes_enable(false);
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ret = stm32aes_setup_cr(mode, encrypt);
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if (ret < 0)
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{
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goto out;
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}
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stm32aes_setkey(key, keysize);
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if (iv != NULL)
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{
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stm32aes_setiv(iv);
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}
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stm32aes_enable(true);
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while (size)
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{
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stm32aes_encryptblock(out, in);
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out = (FAR uint8_t *)out + AES_BLOCK_SIZE;
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in = (FAR uint8_t *)in + AES_BLOCK_SIZE;
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size -= AES_BLOCK_SIZE;
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}
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stm32aes_enable(false);
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out:
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nxsem_post(&g_stm32aes_lock);
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return ret;
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}
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