412 lines
13 KiB
C
412 lines
13 KiB
C
/****************************************************************************
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* arch/arm/src/imxrt/imxrt_irq.c
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*
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* Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <errno.h>
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#include "up_arch.h"
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#include "hardware/imxrt_ccm.h"
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#include "imxrt_periphclks.h"
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#include "imxrt_iomuxc.h"
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This table is indexed by the Pad Mux register index and provides the index
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* to the corresponding Pad Control register.
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*
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* REVISIT: This could be greatly simplified: The Pad Control registers
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* map 1-to-1 with the Pad Mux registers except for two regions where
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* there are no corresponding Pad Mux registers. The entire table could be
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* replaced to two range checks and the appropriate offset added to the Pad
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* Mux Register index.
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*/
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#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
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static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
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{
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/* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */
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IMXRT_PADCTL_GPIO_EMC_00_INDEX,
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IMXRT_PADCTL_GPIO_EMC_01_INDEX,
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IMXRT_PADCTL_GPIO_EMC_02_INDEX,
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IMXRT_PADCTL_GPIO_EMC_03_INDEX,
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IMXRT_PADCTL_GPIO_EMC_04_INDEX,
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IMXRT_PADCTL_GPIO_EMC_05_INDEX,
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IMXRT_PADCTL_GPIO_EMC_06_INDEX,
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IMXRT_PADCTL_GPIO_EMC_07_INDEX,
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IMXRT_PADCTL_GPIO_EMC_08_INDEX,
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IMXRT_PADCTL_GPIO_EMC_09_INDEX,
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IMXRT_PADCTL_GPIO_EMC_10_INDEX,
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IMXRT_PADCTL_GPIO_EMC_11_INDEX,
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IMXRT_PADCTL_GPIO_EMC_12_INDEX,
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IMXRT_PADCTL_GPIO_EMC_13_INDEX,
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IMXRT_PADCTL_GPIO_EMC_14_INDEX,
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IMXRT_PADCTL_GPIO_EMC_15_INDEX,
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IMXRT_PADCTL_GPIO_EMC_16_INDEX,
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IMXRT_PADCTL_GPIO_EMC_17_INDEX,
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IMXRT_PADCTL_GPIO_EMC_18_INDEX,
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IMXRT_PADCTL_GPIO_EMC_19_INDEX,
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IMXRT_PADCTL_GPIO_EMC_20_INDEX,
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IMXRT_PADCTL_GPIO_EMC_21_INDEX,
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IMXRT_PADCTL_GPIO_EMC_22_INDEX,
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IMXRT_PADCTL_GPIO_EMC_23_INDEX,
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IMXRT_PADCTL_GPIO_EMC_24_INDEX,
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IMXRT_PADCTL_GPIO_EMC_25_INDEX,
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IMXRT_PADCTL_GPIO_EMC_26_INDEX,
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IMXRT_PADCTL_GPIO_EMC_27_INDEX,
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IMXRT_PADCTL_GPIO_EMC_28_INDEX,
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IMXRT_PADCTL_GPIO_EMC_29_INDEX,
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IMXRT_PADCTL_GPIO_EMC_30_INDEX,
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IMXRT_PADCTL_GPIO_EMC_31_INDEX,
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IMXRT_PADCTL_GPIO_EMC_32_INDEX,
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IMXRT_PADCTL_GPIO_EMC_33_INDEX,
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IMXRT_PADCTL_GPIO_EMC_34_INDEX,
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IMXRT_PADCTL_GPIO_EMC_35_INDEX,
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IMXRT_PADCTL_GPIO_EMC_36_INDEX,
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IMXRT_PADCTL_GPIO_EMC_37_INDEX,
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IMXRT_PADCTL_GPIO_EMC_38_INDEX,
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IMXRT_PADCTL_GPIO_EMC_39_INDEX,
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IMXRT_PADCTL_GPIO_EMC_40_INDEX,
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IMXRT_PADCTL_GPIO_EMC_41_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_00_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_01_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_02_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_03_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_04_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_05_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_06_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_07_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_08_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_09_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_10_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_11_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_12_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_13_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_14_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_15_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_00_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_01_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_02_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_03_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_04_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_05_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_06_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_07_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_08_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_09_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_10_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_11_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_12_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_13_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_14_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_15_INDEX,
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IMXRT_PADCTL_GPIO_B0_00_INDEX,
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IMXRT_PADCTL_GPIO_B0_01_INDEX,
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IMXRT_PADCTL_GPIO_B0_02_INDEX,
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IMXRT_PADCTL_GPIO_B0_03_INDEX,
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IMXRT_PADCTL_GPIO_B0_04_INDEX,
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IMXRT_PADCTL_GPIO_B0_05_INDEX,
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IMXRT_PADCTL_GPIO_B0_06_INDEX,
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IMXRT_PADCTL_GPIO_B0_07_INDEX,
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IMXRT_PADCTL_GPIO_B0_08_INDEX,
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IMXRT_PADCTL_GPIO_B0_09_INDEX,
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IMXRT_PADCTL_GPIO_B0_10_INDEX,
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IMXRT_PADCTL_GPIO_B0_11_INDEX,
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IMXRT_PADCTL_GPIO_B0_12_INDEX,
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IMXRT_PADCTL_GPIO_B0_13_INDEX,
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IMXRT_PADCTL_GPIO_B0_14_INDEX,
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IMXRT_PADCTL_GPIO_B0_15_INDEX,
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IMXRT_PADCTL_GPIO_B1_00_INDEX,
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IMXRT_PADCTL_GPIO_B1_01_INDEX,
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IMXRT_PADCTL_GPIO_B1_02_INDEX,
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IMXRT_PADCTL_GPIO_B1_03_INDEX,
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IMXRT_PADCTL_GPIO_B1_04_INDEX,
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IMXRT_PADCTL_GPIO_B1_05_INDEX,
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IMXRT_PADCTL_GPIO_B1_06_INDEX,
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IMXRT_PADCTL_GPIO_B1_07_INDEX,
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IMXRT_PADCTL_GPIO_B1_08_INDEX,
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IMXRT_PADCTL_GPIO_B1_09_INDEX,
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IMXRT_PADCTL_GPIO_B1_10_INDEX,
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IMXRT_PADCTL_GPIO_B1_11_INDEX,
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IMXRT_PADCTL_GPIO_B1_12_INDEX,
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IMXRT_PADCTL_GPIO_B1_13_INDEX,
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IMXRT_PADCTL_GPIO_B1_14_INDEX,
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IMXRT_PADCTL_GPIO_B1_15_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_00_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_01_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_02_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_03_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_04_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_05_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_00_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_01_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_02_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_03_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_04_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_05_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_06_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_07_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_08_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_09_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_10_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_11_INDEX,
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IMXRT_PADCTL_WAKEUP_INDEX,
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IMXRT_PADCTL_PMIC_ON_REQ_INDEX,
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IMXRT_PADCTL_PMIC_STBY_REQ_INDEX
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};
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#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
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static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
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{
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/* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */
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IMXRT_PADCTL_GPIO_EMC_00_INDEX,
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IMXRT_PADCTL_GPIO_EMC_01_INDEX,
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IMXRT_PADCTL_GPIO_EMC_02_INDEX,
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IMXRT_PADCTL_GPIO_EMC_03_INDEX,
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IMXRT_PADCTL_GPIO_EMC_04_INDEX,
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IMXRT_PADCTL_GPIO_EMC_05_INDEX,
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IMXRT_PADCTL_GPIO_EMC_06_INDEX,
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IMXRT_PADCTL_GPIO_EMC_07_INDEX,
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IMXRT_PADCTL_GPIO_EMC_08_INDEX,
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IMXRT_PADCTL_GPIO_EMC_09_INDEX,
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IMXRT_PADCTL_GPIO_EMC_10_INDEX,
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IMXRT_PADCTL_GPIO_EMC_11_INDEX,
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IMXRT_PADCTL_GPIO_EMC_12_INDEX,
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IMXRT_PADCTL_GPIO_EMC_13_INDEX,
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IMXRT_PADCTL_GPIO_EMC_14_INDEX,
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IMXRT_PADCTL_GPIO_EMC_15_INDEX,
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IMXRT_PADCTL_GPIO_EMC_16_INDEX,
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IMXRT_PADCTL_GPIO_EMC_17_INDEX,
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IMXRT_PADCTL_GPIO_EMC_18_INDEX,
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IMXRT_PADCTL_GPIO_EMC_19_INDEX,
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IMXRT_PADCTL_GPIO_EMC_20_INDEX,
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IMXRT_PADCTL_GPIO_EMC_21_INDEX,
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IMXRT_PADCTL_GPIO_EMC_22_INDEX,
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IMXRT_PADCTL_GPIO_EMC_23_INDEX,
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IMXRT_PADCTL_GPIO_EMC_24_INDEX,
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IMXRT_PADCTL_GPIO_EMC_25_INDEX,
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IMXRT_PADCTL_GPIO_EMC_26_INDEX,
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IMXRT_PADCTL_GPIO_EMC_27_INDEX,
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IMXRT_PADCTL_GPIO_EMC_28_INDEX,
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IMXRT_PADCTL_GPIO_EMC_29_INDEX,
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IMXRT_PADCTL_GPIO_EMC_30_INDEX,
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IMXRT_PADCTL_GPIO_EMC_31_INDEX,
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IMXRT_PADCTL_GPIO_EMC_32_INDEX,
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IMXRT_PADCTL_GPIO_EMC_33_INDEX,
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IMXRT_PADCTL_GPIO_EMC_34_INDEX,
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IMXRT_PADCTL_GPIO_EMC_35_INDEX,
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IMXRT_PADCTL_GPIO_EMC_36_INDEX,
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IMXRT_PADCTL_GPIO_EMC_37_INDEX,
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IMXRT_PADCTL_GPIO_EMC_38_INDEX,
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IMXRT_PADCTL_GPIO_EMC_39_INDEX,
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IMXRT_PADCTL_GPIO_EMC_40_INDEX,
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IMXRT_PADCTL_GPIO_EMC_41_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_00_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_01_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_02_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_03_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_04_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_05_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_06_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_07_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_08_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_09_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_10_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_11_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_12_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_13_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_14_INDEX,
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IMXRT_PADCTL_GPIO_AD_B0_15_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_00_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_01_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_02_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_03_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_04_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_05_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_06_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_07_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_08_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_09_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_10_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_11_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_12_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_13_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_14_INDEX,
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IMXRT_PADCTL_GPIO_AD_B1_15_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_00_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_01_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_02_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_03_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_04_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_05_INDEX,
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IMXRT_PADCTL_GPIO_SD_B0_06_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_00_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_01_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_02_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_03_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_04_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_05_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_06_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_07_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_08_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_09_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_10_INDEX,
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IMXRT_PADCTL_GPIO_SD_B1_11_INDEX,
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IMXRT_PADCTL_WAKEUP_INDEX,
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IMXRT_PADCTL_PMIC_ON_REQ_INDEX,
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IMXRT_PADCTL_PMIC_STBY_REQ_INDEX
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};
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#else
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#error Unrecognised IMXRT family
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: imxrt_padmux_map
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*
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* Description:
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* This function map a Pad Mux register index to the corresponding Pad
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* Control register index.
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*
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****************************************************************************/
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unsigned int imxrt_padmux_map(unsigned int padmux)
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{
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DEBUGASSERT(padmux < IMXRT_PADMUX_NREGISTERS);
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return (unsigned int)g_mux2ctl_map[padmux];
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}
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/****************************************************************************
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* Name: imxrt_iomux_configure
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*
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* Description:
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* This function writes the encoded pad configuration to the Pad Control
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* register.
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*
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****************************************************************************/
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int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset)
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{
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uint32_t regval = 0;
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uint32_t value;
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/* Enable IOMUXC clock if it is not already enabled */
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imxrt_clockall_iomuxc();
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imxrt_clockall_iomuxc_gpr();
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#if 0 /* Are low-power domain, Secure Non-volatile Storage (SNVS) IOMUXC clocks needed? */
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imxrt_clockall_iomuxc_snvs();
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imxrt_clockall_iomuxc_snvs_gpr();
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#endif
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/* Select CMOS input or Schmitt Trigger input */
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regval = 0;
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if ((ioset & IOMUX_SCHMITT_TRIGGER) != 0)
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{
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regval |= PADCTL_HYS;
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}
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/* Select drive strength */
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value = (ioset & IOMUX_DRIVE_MASK) >> IOMUX_DRIVE_SHIFT;
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regval |= PADCTL_DSE(value);
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/* Select spped */
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value = (ioset & IOMUX_SPEED_MASK) >> IOMUX_SPEED_SHIFT;
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regval |= PADCTL_SPEED(value);
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/* Select CMOS output or Open Drain outpout */
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if ((ioset & IOMUX_OPENDRAIN) != 0)
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{
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regval |= PADCTL_ODE;
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}
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/* Handle pull/keep selection */
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switch (ioset & _IOMUX_PULLTYPE_MASK)
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{
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default:
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case _IOMUX_PULL_NONE:
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break;
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case _IOMUX_PULL_KEEP:
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{
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regval |= PADCTL_PKE;
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}
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break;
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case _IOMUX_PULL_ENABLE:
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{
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regval |= (PADCTL_PKE | PADCTL_PUE);
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value = (ioset & _IOMUX_PULLDESC_MASK) >> _IOMUX_PULLDESC_SHIFT;
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regval |= PADCTL_PUS(value);
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* Select slow/fast slew rate */
|
|
|
|
if ((ioset & IOMUX_SLEW_FAST) != 0)
|
|
{
|
|
regval |= PADCTL_SRE;
|
|
}
|
|
|
|
/* Write the result to the specified Pad Control register */
|
|
|
|
putreg32(regval, padctl);
|
|
return OK;
|
|
}
|