5d4e4b1919
RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain. For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c] For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c] So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by all LLVM based toolchain. Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td These models can't cover all implementation of RISCV, but it's enough for most cases. Signed-off-by: Huang Qi <huangqi3@xiaomi.com> |
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