7a9457bb07
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5145 42af7a65-404d-4744-a932-0658087f49c3
113 lines
5.4 KiB
C
113 lines
5.4 KiB
C
/************************************************************************************
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* arch/avr/src/at32uc3/at32uc3_rtc.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H
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#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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#define AVR32_RTC_CTRL_OFFSET 0x00 /* Control Register */
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#define AVR32_RTC_VAL_OFFSET 0x04 /* Value Register */
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#define AVR32_RTC_TOP_OFFSET 0x08 /* Top Register */
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#define AVR32_RTC_IER_OFFSET 0x10 /* Interrupt Enable Register */
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#define AVR32_RTC_IDR_OFFSET 0x14 /* Interrupt Disable Register */
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#define AVR32_RTC_IMR_OFFSET 0x18 /* Interrupt Mask Register */
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#define AVR32_RTC_ISR_OFFSET 0x1c /* Interrupt Status Register */
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#define AVR32_RTC_ICR_OFFSET 0x20 /* Interrupt Clear Register */
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/* Register Addresses ***************************************************************/
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#define AVR32_RTC_CTRL (AVR32_RTC_BASE+AVR32_RTC_CTRL_OFFSET)
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#define AVR32_RTC_VAL (AVR32_RTC_BASE+AVR32_RTC_VAL_OFFSET)
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#define AVR32_RTC_TOP (AVR32_RTC_BASE+AVR32_RTC_TOP_OFFSET)
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#define AVR32_RTC_IER (AVR32_RTC_BASE+AVR32_RTC_IER_OFFSET)
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#define AVR32_RTC_IDR (AVR32_RTC_BASE+AVR32_RTC_IDR_OFFSET)
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#define AVR32_RTC_IMR (AVR32_RTC_BASE+AVR32_RTC_IMR_OFFSET)
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#define AVR32_RTC_ISR (AVR32_RTC_BASE+AVR32_RTC_ISR_OFFSET)
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#define AVR32_RTC_ICR (AVR32_RTC_BASE+AVR32_RTC_ICR_OFFSET)
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/* Register Bit-field Definitions ***************************************************/
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/* Control Register Bit-field Definitions */
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#define RTC_CTRL_EN (1 << 0) /* Bit 0: Enable */
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#define RTC_CTRL_PCLR (1 << 1) /* Bit 1: Prescaler Clear */
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#define RTC_CTRL_WAKEN (1 << 2) /* Bit 2: Wakeup Enable */
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#define RTC_CTRL_CLK32 (1 << 3) /* Bit 3: 32 KHz Oscillator Select */
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#define RTC_CTRL_BUSY (1 << 4) /* Bit 4: RTC Busy */
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#define RTC_CTRL_PSEL_SHIFT (8) /* Bits 8-11: Prescale Select */
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#define RTC_CTRL_PSEL_MASK (15 << RTC_CTRL_PSEL_SHIFT)
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#define RTC_CTRL_CLKEN (1 << 16) /* Bit 16: Clock Enable */
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/* Value Register Bit-field Definitions */
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/* This is a 32-bit data register and, hence, has no bit field */
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/* Top Register Bit-field Definitions */
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/* This is a 32-bit data register and, hence, has no bit field */
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/* Interrupt Enable Register Bit-field Definitions
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* Interrupt Disable Register Bit-field Definitions
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* Interrupt Mask Register Bit-field Definitions
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* Interrupt Status Register Bit-field Definitions
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* Interrupt Clear Register Bit-field Definitions
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*/
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#define RTC_INT_TOPI (1 << 0) /* Bit 0: Top interrupt */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H */
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