Jari Nippula 6ba906691a clear spi int before the transfer starts ... In spi_irq handler the data is written into txfifo and transfer is started before the TXDONE interrupt is cleared. If the bus/memory access is in some cases delayed, the spi transfer may have been finished already before the interrupt register is cleaned for the transfer. This leads the early arrived interrupt to be just removed and never handled, which would cause a timeout error. This patch moves the clearing of the interrupt to the place before the tx is started, so the interrupt is not missed in above cases.		2023-03-02 22:05:25 +08:00
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include	Remove the tail spaces from all files except Documentation	2023-02-26 13:24:24 -08:00
src	clear spi int before the transfer starts	2023-03-02 22:05:25 +08:00
Kconfig	risc-v/esp32c6: Add ESP32-C6 basic support	2023-02-10 17:38:41 -03:00